Instruction decoding in data processing apparatus

Abstract

An instruction decoding system for data processing apparatus in which alternative instruction interpretations are made possible through hardware sensing of the operational state of one or more machine elements. In one embodiment, a zero detect unit is used to sense the state of a subroutine stack used in a microprogrammed system, therefore permitting a generic "exit" microcommand to be interpreted either as a "return" or a "decode" depending upon the state of the subroutine stack.

Having thus described a preferred embodiment of the invention, what is claimed is: 
     
       1. An instruction decoding system for a data processing apparatus in which alternative instruction interpretations are dependent upon the operational state of at least a part of said apparatus comprising: instruction register means (25, 26) for storing an instruction;   subroutine stack means (27, 28) for generating a generic exit signal which can indicate either a return command or a decode command;   detection means (34) for detecting the status of said stack means and producing a control signal representative of said status;   instruction decoding means (29, 30, 36, 37, 38) connected to said instruction register means and to said detection means and functioning to produce instruction execution signals based upon the combination of said instruction and said control signal from said detection means in order to determine whether said exit signal is a return command or a decode command in response to said control signal; and   an arithmetic or logical function means (39) having an input connected to said instruction decoding means and responsive to said instruction execution signals to perform a predetermined arithmetic or logical operation.   
     
     
       2. The system recited in claim 1 wherein, said stack means includes stack memory means storing a subroutine including said exit signal and stack address means for storing the addresses of said subroutine,   said detection means connected to detect the status of said stack address means in terms of being empty or not.   
     
     
       3. The system recited in claim 1 wherein, said detection means means is a zero detect unit. 
     
     
       4. The system recited in claim 1 including, a microaddress control unit (35) connected to receive a signal from said detection (34) means, and wherein said instruction decoding means includes,   a control store device (29, 36, 37) for addressing and storing micro instruction words,   said microaddress control unit (35) connected to provide an input to said control store device (29, 36, 37) depending upon the control signal representative of said status.   
     
     
       5. The system recited in claim 4 wherein, said control store device includes a control store unit (37) for storing microinstructions and a control store address register (36) connected to said control store unit (37).   
     
     
       6. The system recited in claim 4 wherein said subroutine stack means includes stack memory means, and multiplexer means connected to receive signals from said stack memory means and from said microaddress control unit,   said multiplexer means connected to selectively supply signals received thereby to said control store device.   
     
     
       7. The system recited in claim 6 wherein, said multiplexer means is connected to receive signals from said microaddress control unit to determine the operation of said multiplexer means in passing signals therethrough to said control store device.   
     
     
       8. The data processing system recited in claim 6 wherein, said stack memory means comprises a last-in, first-out (LIFO) stack register.   
     
     
       9. The system recited in claim 8 including, said stack register having a full operational state and an empty operational state,   said detection means connected to said stack register and selectively producing stack status signals representing said full state or said empty state of said stack register.   
     
     
       10. The system recited in claim 9 wherein, said stack register includes a stack address register and a subroutine stack memory. 
     
     
       11. The system recited in claim 10 wherein, said stack memory comprises a RAM. 
     
     
       12. The system recited in claim 9 wherein, said stack status signal is supplied to said arithmetic and logical function means.