Bootstrap driver circuit

Abstract

A MOS two-phase boostrap driver circuit, having a bootstrap transistor with a gate selectively charged or discharged in response to the level of an input signal, provides for selectively charging the gate of the bootstrap transistor directly from a voltage supply.

I claim: 
     
       1. A two-phase field effect transistor circuit for selectively providing an output signal on an output line in response to an input signal comprising: means for providing a reference voltage;   means for providing a supply voltage;   means for providing alternating first and second clock signals;   a first transistor having a gate coupled to receive the input signal, a first terminal coupled to receive the supply voltage and a second terminal;   a second transistor having a gate coupled to receive the second clock signal, a first terminal coupled to the gate of the first transistor, and a second terminal coupled to the second terminal of the first transistor;   a third transistor having a gate coupled to receive the second clock signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal;   a fourth transistor having a gate coupled to receive the second clock signal, a first terminal coupled to the output line, and a second terminal coupled to receive the reference voltage;   a fifth transistor having a gate coupled to the second terminal of the third transistor, a first terminal coupled to the output line and a second terminal coupled to receive the first clock signal; and   means for providing a capacitance between the gate of the fifth transistor and the output line.   
     
     
       2. A two-phase circuit for selectively providing an output signal as in claim 1 further comprising: capacitive means coupled to the gate of the first transistor for capacitively storing signals applied thereto:   a sixth transistor having a gate coupled to receive the first clock signal, a first terminal coupled to receive the supply voltage, and a second terminal coupled to the capacitive means; and   a seventh transistor having a gate coupled to receive a control signal, a first terminal coupled to the capacitive means, and a second terminal coupled to receive the reference voltage.   
     
     
       3. A MOS integrated memory circuit for providing data signals representative of a data word selected in response to an address signal comprising a plurality of two-phase circuits as in claim 1 and further comprising an address decoder coupled to the two-phase circuits for providing an input signal to one of the two-phase circuits selected in response to the value of the address signal; and memory means for providing data signals representative of a data word selected in response to an output signal from the selected two-phase circuit.   
     
     
       4. A two-phase circuit as in claims 1 or 2 wherein the threshold voltages of the transistors, the amplitude of the supply voltage and the high voltage level of the second clock signal are such that the second transistor is in a nonconductive state in response to the second clock signal when the first and second terminals of the second transistor are at voltage levels substantially equal to the supply voltage and in a conductive state in response to the second clock signal when the first or second terminal of the second transistor is at a voltage level substantially equal to the reference voltage. 
     
     
       5. A two-phase circuit as in claim 2 integrated on a single chip wherein the first, third and sixth transistors have a voltage threshold which is less than the voltage threshold of the second transistor.