Process for aligning diffusion masks with respect to isolating walls of coffers in integrated circuits

Abstract

A process in which P + impurities are implanted in a P silicon substrate at the periphery of N + buried layers, prior to growing an N epitaxial layer. Then an upward diffusion of the P + impurities is caused up to the surface of the wafer in order to form insulation walls insulating separate N coffers. An anodization followed with an oxidation transforms those P walls into silica walls and makes their upper surface visible.

What is claimed is: 
     
       1. A process for aligning diffusion masks with respect to isolating walls of coffers in integrated circuits, these coffers being formed in a layer having a first type of conductivity and a thickness less than 3 microns obtained by epitaxial growth on a substrate having a second type of conductivity in which there are implanted, in zones corresponding to the bottom of the coffers, doping impurities of the first type of conductivity, these coffers being limited laterally by isolating walls; the improvement comprising implanting doping impurities of the second type of conductivity in the substrate along the contour of the isolating walls and then after formation of the epitaxial layer in causing these impurities to diffuse towards and as far as the surface of the epitaxial layer; and further comprising the step which consists in making the upper surface flush zone of the insulating walls visible at the surface of the epitaxial layer in order to facilitate alignment. 
     
     
       2. The process as claimed in claim 1, wherein the thickness of the epitaxial layer is less than 1 micron. 
     
     
       3. The process as claimed in claim 1, comprising the further steps of anodizing the wafers so as to transform the isolating walls made of monocrystalline silicon having the same type of conductivity as the substrate, into porous silicon, then of proceeding with an oxidizing treatment so as to transform the porous silicon into silica. 
     
     
       4. The process as claimed in claim 3, wherein the foundations of the isolating walls are disposed so as to come laterally into contact with the periphery of the buried layer having the first type of conductivity, after diffusion. 
     
     
       5. The process as claimed in claim 4 further comprising forming adjacent coffers and the forming an NPN transistor in one of the coffers and a PNP-substrate transistor in the adjacent coffer. 
     
     
       6. The process as claimed in claim 1, comprising the further step of submitting the surface of the wafer to chemical etching, selective according to the type of conductivity. 
     
     
       7. The process as claimed in claim 1, wherein the first doping impurities are arsenic and the second boron.