Variable-gain differential amplifier

Abstract

A variable-gain differential amplifier comprises a first long-tailed transistor pair between the bases of which the input signal is applied. The emitter-collector paths of the transistors of the first pair are included in the tails of second and third long-tailed transistor pairs respectively, and load resistors between the lower terminals of which the output signal appears are included in the respective collector circuits of one transistor of each of the second and third pairs, and hence in the collector circuits of the respective transistors of the first pair. The second and third pairs are controlled by a gain control signal thereby diverting a variable proportion of the collector signal currents of the transistors of the first pair away from the load resistors (17,18) and hence varying the gain of the circuit. In order that variations in the gain control signal should not affect the d.c. level at the amplifier output the collectors of the other transistors of the second and third pairs are commoned and connected to the input of a current splitter the two output currents of which are fed to the respective load resistors, thereby compensating for any changes in the standing currents through the load resistors which would otherwise be produced by changes in the gain control voltage.

What is claimed is: 
     
       1. A variable-gain differential amplifier circuit arrangement comprising: first and second long-tailed pairs of transistors, a control input, a current source circuit for controlling said control input to which said amplifier input is coupled, said current source circuit having first and second output current paths included in the tails of said first and second said long-tailed pairs respectively and being constructed so that the currents in said output current paths will vary in mutually opposite sense in response to the application of a signal to said amplifier input, first and second d.c. load impedances included in the output elecrode circuits of one transistor of said first pair and one transistor of said second pair respectively, a gain control input coupled to the control electrodes of the transistors of said first and second pairs in such manner that the application of a gain control signal to said input will result in said one transistor of said first pair and said one transistor of said second pair being driven in the same sense and in the other transistor of said first pair and the other transistor of said second pair being driven in the opposite sense, and   means for maintaining the standing voltages at those terminals of said load impedances which are connected to the output electrodes of the one transistor of said first pair and the one transistor of said second pair respectively substantially independent of the value of said gain control signal,   wherein said means comprises a current divider circuit to the input of which are connected to output electrodes of said other transistors of said first and second pairs, said current divider circuit having first and second outputs connected to said terminal of said first load impedance and said terminal of said second load impedance respectively.   
     
     
       2. An arrangement as claimed in claim 1, wherein said current divider circuit comprises a further transistor the input electrode of which is connected to said divider circuit input and the output electrode of which is connected to one of the divider circuit outputs, and a semiconductor junction included between the divider circuit input and the other of the divider circuit outputs, said semiconductor junction being connected between the control electrode of said further transistor and the divider circuit input in such a sense that it has the same polarity, as seen from the divider circuit input, as has the control electrode-input electrode junction of said further transistor. 
     
     
       3. An arrangement as claimed in claim 1, wherein said semiconductor junction is the control electrode-input electrode junction of a second further transistor which is of the same conductivity type as said further transistor and which has its output electrode connected to its control electrode, and wherein said first and second resistors are included in the connections between the divider circuit input and the input electrodes of said further transistor and said second further transistor respectively. 
     
     
       4. An arrangement as claimed in claim 2 or claim 3, wherein said first and second load impedances are formed by the input circuits of first and second current repeater circuits respectively, each of said current repeater circuit having an input current path between an input terminal thereof and being constructed to respond to the passage of a current through its input current path by carrying a current in its output current path which is linearly proportional to the current carried by its input current path and has the same sense with respect to its sum terminal as has the current carried by its input current path, the input terminals of the first and second current repeater circuits constituting the said terminals of said first and second load impedances respectively. 
     
     
       5. An arrangement as claimed in claim 1, wherein said current divider circuit comprises first and second further transistors connected to the input electrodes to which said divider circuit input is connected via first and second resistors respectively and the output electrodes of which are connected to the first and second outputs of said current divider circuit respectively, the control electrodes of said further transistors being connected to a constant potential point. 
     
     
       6. An arrangement as claimed in claim 5, wherein said output electrodes of said one transistor of said first pair and said one transistor of said second pair are connected to the input electrodes of the first and second further transistors respectively so that the connections of these output electrodes to the first and second load impedances respectively are via the output electrode-input electrode paths of said first and second further transistors respectively. 
     
     
       7. An arrangement as claimed in claim 1 wherein said output electrodes of said one transistor of said first pair and said one transistor of said second pair are connected directly to said first and second load impedances respectively.