Memory circuit with means for compensating for inversion of stored data

Abstract

Information stored in a reference cell is inverted when the information stored in a memory cell is inverted. The memory cell information is derived from a first Exclusive OR gate receptive of an input data signal and the reference cell output signal. Information is read out of the memory cell via a second Exclusive-OR gate receptive of the output of the memory cell and the output of the reference cell. Regardless of any inversion within the memory cell, the signal produced at the output of the second Exclusive OR gate is of the same binary significance as the input data applied to the first Exclusive-OR gate.

What is claimed is: 
     
       1. The combination comprising: a memory cell having an input-output terminal and having a volatile section and a non-volatile section including means for transferring information between the volatile and non-volatile section and wherein the contents of said memory cell undergo an inversion when information transferred from said volatile section to said non-volatile section is recalled from said non-volatile section into said volatile section;   a reference cell having an output point, said reference cell being keyed to said memory cell whereby the contents of said reference cell undergo an inversion whenever the contents of said memory cell undergo an inversion;   a data bus adapted to receive an input data signal;   first, and second gate means, each gate means having two inputs and an output and each being responsive to the signals at its two inputs for producing a signal of first binary significance when its two inputs are of like binary value and for producing a signal of second binary significance when its two inputs are of different binary value;   means coupling the inputs of said first gate means to the output of said reference cell and to said data bus and its output to the input-output point of said memory cell; and   means coupling the inputs of said second gating means to the output of said reference cell and to the input-output terminal of said memory cell for producing at the output of said second gating means a signal having the same binary significance as said input data signal.   
     
     
       2. The combination as claimed in claim 1, wherein said first gate means includes a first logic gate having two inputs and an output and a first control gate having two inputs and an output, one input of said control gate being connected to the output of said first logic gate and the other input of said control gate being connected to a control signal for selectively enabling the transfer of the output of said first logic gate to said input-output point of said memory cell; and wherein said means coupling the inputs of said first gate means includes means connecting one input of said first logic gate to said data bus and means connecting the other input of said first logic gate to said output point of said reference cell.   
     
     
       3. The combination as claimed in claim 2 wherein said second gate means includes a second logic gate having two inputs and an output and a second control gate having two inputs and an output, one input of said second control gate being connected to the output of said logic gate and the other input of said control gate being connected to a control signal or selectively enabling the transfer of the output of said second logic gate to a data-output point; and wherein said means coupling the outputs of said second gate means includes means coupling one input of said second logic gate to said input-out point of said memory cell and means connecting the other input of said second logic gate to said output point of said reference cell.   
     
     
       4. The combination as claimed in claim 1 wherein said means for transferring information between the volatile and non-volatile sections of said memory cell and reference cell include means for transferring the contents within said memory cell and for causing a like transfer within said reference cell. 
     
     
       5. The combination as claimed in claim 4 wherein said means for transferring information between the volatile and non-volatile sections of said cells includes means for transferring information from the non-volatile section to the volatile section, and means for recalling information from the non-volatile section to the volatile section. 
     
     
       6. The combination as claimed in claim 1 wherein said volatile section of said memory cell has an internal input-output node; and wherein said memory cell includes a controllable gating transistor having a conduction path and a control electrode, wherein the conduction path of said gating transistor is connected between said internal input-output node and said input-output terminal for enabling writing of new information into the memory cell from said input-output point and the reading-out of the contents of the memory cell onto said input-output point.   
     
     
       7. In combination with a memory cell having a volatile section and non-volatile section including means for transferring information between the volatile and non-volatile section and wherein the contents of said memory cell undergo an inversion when information transferred from said volatile section to said non-volatile section is recalled from said non-volatile section into said volatile section; a circuit for writing information into the memory cell corresponding to a data input signal on a data bus and for subsequently reading the information stored in the memory cell and producing a data output signal of like significance to said data input comprising: a reference cell having an output, and also of the type whose contents can be inverted;   means coupled to said memory cell and to said reference cell for inverting the information stored in the reference cell when the information stored in said memory cell undergoes said given inversion;   first means responsive to said data input signal ("D") on said data bus and to the signal ("C") at said output of said reference cell for producing a first output signal having one binary value when "D" and "C" have the same binary values and the other binary value when "C" and "D" have different binary values;   means for selectively writing said output of said first means into said memory cell for storage in said memory cell; and   second means for reading out the contents of the memory cell and for producing a second output, of like binary significance to the value of said data input signal; said second means having one input "M" responsive to the output of said memory cell and another input "N" responsive to the output of said reference and said second means being of the type which produces an output having one binary value when M and N have like binary values and an output having the other binary value when "M" and "N" have different binary values, whereby the input of said second means is of like binary significance to said input signal D.   
     
     
       8. In combination: a memory cell having an input-output terminal and having a volatile section and a non-volatile section including means for transferring information between the volatile and non-volatile section and wherein the contents of said memory cell undergo an inversion when information transferred from said volatile section to said non-volatile section is recalled from said non-volatile section into said volatile section;   a reference cell having an output terminal, and also of the type whose contents can be inverted;   means coupled to said memory cell and to said reference cell for inverting the information stored in the reference cell whenever the information stored in said memory cell is inverted; and   first and second gates, each one of said gates being of the type which produces at its output a signal which is the parity function of its inputs, where the parity function is equal to the least significant bit of the sum of the gate inputs, said first gate receptive of the signal present at the output terminal of said reference cell and an input data signal and applying its output to said input-output terminal of said memory cell for writing into said memory cell, and said second gate receptive of a signal present on said input-output terminal of said memory cell and the signal present at the output terminal of said reference cell, and applying its output to the terminal of said first gate receptive of said data signal.   
     
     
       9. The combination as claimed in claim 8 wherein each one of said first and second gates is a two input gate which produces at its output a signal of first binary significance when its two inputs have the same binary values and a signal of second binary significance when its two inputs have different binary values. 
     
     
       10. The combination as claimed in claim 9 wherein said first and second gates are Exclusive OR gates.