Semiconductor circuit for speed control of electric motors

Abstract

A digital control loop is provided in which analog signals supplied by a tachometer, driven by an electric motor, are digitally evaluated, that is are compared with a reference value existing in digital form, and a deviation from the reference is employed for controlling the adjustment of an element, a thyristor preferably a triac, by way of an adjusting value generator which is likewise designed as a digital circuit. The speed control regulator can be designed both with an integral control behavior, and a differential control behavior, as well as being designed with a proportional control behavior and combinations thereof.

We clam: 
     
       1. A speed control circuit for controlling the speed of an a.c. electric motor which is connected to a supply voltage and has a drive shaft and drives a tachometer, comprising: a firing angle control circuit connecting the motor to the supply voltage;   analog/digital converter means including a Schmitt trigger circuit connected to and operated by the tachometer to produce pulses representing actual speed;   first memory means connected to said analog/digital converter means for storing a digital actual speed signal in response to said pulses;   second memory means for storing a digital reference speed signal;   comparison means connected to said first and second memory means for producing an error signal in response to and in accordance with the difference between the digital actual and reference signals;   digital correction means connected to said comparison means and to said firing angle control circuit for producing a firing angle control signal in accordance with the error signal; and   clock means connnected to the supply voltage and to said analog/digital converter means and to said correction means and operable to produce clock pulses to synchronize the operation of said control circuit.   
     
     
       2. The control circuit of claim 1, wherein said analog/digital converter means comprises: a gate including a first input connected to said clock means, a second input connected to said Schmitt trigger, a third input and an output;   a clock pulse evaluation circuit connected to said clock means and to said Schmitt trigger circuit for scanning the output of said Schmitt trigger circuit;   a counter connected to said output of said gate and connected to said clock pulse evaluation circuit and operated to receive a digital word and provide the word to said first memory means as the digital actual speed control signal.   
     
     
       3. The control circuit of claim 2, wherein: said comparison means comprises a comparator connected between said first and second memory means.   
     
     
       4. The control circuit of claim 3, wherein said correction means comprises a revolution counter means connected to and controlled by said clock means;   a regulating counter means connected to and controlled by said comparator; and   another comparator connected to and operated in response to said revolution and regulating counters to provide said firing angle control signal to said firing angle control circuit.   
     
     
       5. The control circuit of clam 4, wherein: said correction means comprises a programmable read-only memory for receiving the error signal and the output of said second memory means; and   a digital counter connected to the output of said programmable read-only memory for inputting information to said regulating counter.   
     
     
       6. The control circuit of claim 4, wherein: said correction means comprises a read-only memory;   a clock-controlled digital counter connected to said clock means and to said comparator and connected to feed said regulating counter.   
     
     
       7. The control circuit of claim 6, comprising: a timing circuit having a predetermined time delay, connected between said digital counter and said regulating counter.   
     
     
       8. The control circuit of claim 4, wherein said correction means comprises: first and second intermediate memories;   said first intermediate memory connected to said second memory means and to said comparison means to receive said error signal;   a second intermediate memory connected to and fed by said first intermediate memory;   a further comparator connected to said first and second intermediate memories for comparing the storage contents; and   control means connecting said further comparator to said firing angle control circuit and operable to adjust the firing angle in accordance with the output of said further comparator.   
     
     
       9. The control circuit of claim 1, wherein said control means comprises: a programmed read-only memory connected to said and accessed by said further comparator;   a clock-controlled counter connected to said clock means and to said programmed read-only memory;   a revolution counter connected to and operated by said clock means;   an additional comparator connected to said revolution and regulation counters and operable to provide an ignition pulse to said firing angle control circuit.   
     
     
       10. The control circuit of claim 1, wherein: said first memory means and said second memory means are each constructed as digital counters connected such that one of said counters causes backward counting of the other of said counters so as to also constitute said comparison means.