Deep fat fryer having a solid-state control circuit

Abstract

A solid-state control circuit for selectively operating a deep fat fryer in a normal cook mode, a lower temperature hold mode, a fat melt mode and a safety thermostat test mode. During operation in the cook mode, a reference bias voltage is coupled to one input of a voltage comparator, and an operating bias voltage dependent on the temperature control setting and the actual cooking fat temperature sensed by a NTC resistive sensor is coupled to a second input of the comparator such that the comparator is effective to enable heating elements in the cooking fat when the fat temperature drops below the preset level. After a predetermined time interval during which the fryer is not being used, a timing circuit acts to vary the reference bias voltage and the operating bias voltage supplied to the comparator and thereby reduce the temperature of the fat to the lower preset hold mode temperature. A second comparator resets the timing circuit during the predetermined time interval if there is a demand for heat such as when frozen foodstuffs are placed in the cooking fat. In the melt mode, the timing circuit controls the first comparator such that the heating elements are cycled on and off to melt solidified cooking fat without scorching, and in the test mode, the temperature control potentiometer is bypassed to cause the first comparator to enable the heating elements to safely heat the cooking fat to a temperature where the safety thermostat and the safety contactor should function.

What is claimed is: 
     
       1. In a deep fat fryer having means for establishing a DC voltage differential between a DC power supply line and a reference power supply line and having means including at least two AC power supply lines and one or more heating elements coupled thereto for heating a reservoir of cooking fat, a solid-state control circuit comprising: means coupled to said DC power supply line and said reference power supply line for developing a reference bias potential;   means including operating temperature control means for selecting the temperature at which said cooking fat is to be maintained and means for sensing the temperature of said cooking fat, said temperature control means and said temperature sensing means being coupled in series between said DC power supply line and said reference power supply line and combining to develop an operating bias potential at the junction between said operating temperature control means and said temperature sensing means, the operating bias potential varying responsive to changes in the temperature of said cooking fat to correspond to the temperature of said cooking fat;   means including a voltage comparator coupled to said reference bias means and said operating bias means for comparing the operating bias potential and the reference bias potential and developing an enabling signal whenever the level of the operating bias potential relative to the level of the reference bias potential indicates that the temperature of said cooking fat is below the temperature selected by said operating temperature control means;   said comparator having positive and negative inputs and an output, the positive input of said comparator being coupled to said reference bias means and having the reference bias potential coupled thereto and the negative input of said comparator being coupled to the junction between said operating temperature control means and said temperature sensing means and having the operating bias potential coupled thereto, said comparator developing a low logic level enabling signal at said output whenever the operating bias potential exceeds the reference bias potential;   said temperature sensing means comprises a negative temperature coefficient (NTC) resistive sensor coupled between said operating temperature control means and said reference power supply line, the resistance of said sensor varying inversely with respect to changes in the temperature of said cooking fat to increase the operating bias potential coupled to said comparator such that the operating bias potential exceeds the reference bias potential and said comparator develops a low logic level enabling signal when the temperature of said cooking fat is below the selected temperature level; and   means coupled to said reference bias means and said operating temperature control means for switching said deep fat fryer to operation in a hold mode wherein said cooking fat is maintained at a reduced temperature independently of the temperature selected by said operating temperature control means, said hold mode means altering the reference bias potential and the operating bias potential coupled to said comparator to correspond to the reduced temperature and said comparator developing the enabling signal during operation in the hold mode whenever the level of the altered operating bias potential relative to the level of the altered reference bias potential corresponds to a cooking fat temperature that is below the reduced temperature level.   
     
     
       2. A solid-state control circuit in accordance with claim 1 wherein said reference bias means comprises a plurality of resistors coupled in a voltage divider between said DC power supply line and said reference power supply line and wherein said hold mode means comprises first normally conductive solid-state means coupled in parallel with one of the said plurality of resistors to short said one resistor and second normally off solid-state means coupled in parallel with said operating temperature control means, said hold mode means including timing means for biasing said first solid-state means off and said second solid-state means to conduction to respectively unshort said one resistor and simultaneously short said operating temperature control means at the end of a predetermined time interval during which said deep fat fryer is not in use, and further including automatic resetting means for automatically resetting said timing means to initiate a new predetermined time interval if said deep fat fryer is used before the prior predetermined interval has elapsed. 
     
     
       3. A solid-state control circuit in accordance with claim 2 wherein said timing means comprises oscillator means for generating a series of output pulses at a predetermined frequency, binary counter means having a clock input coupled to said oscillator means and having a plurality of outputs switchable between low logic level states and high logic level states to represent a corresponding count of the number of pulses coupled to said counter, gating means coupled to said binary counter means outputs for decoding the counter output states to provide a single pulse when the counter output states correspond to the end of the predetermined time interval, and bistable means having a reset input coupled to said gating means and a first output coupled to said first solid-state means and said second solid-state means, said bistable means being normally set to bias said first solid-state means on and said second solid-state means off, the single pulse coupled to the reset input of said bistable means at the end of the predetermined time interval resetting said bistable means to bias said first solid-state means off to unshort said one resistor and bias said second solid-state means to conduction to short said operating temperature control means, said deep fat fryer thereafter being operative to maintain said cooking fat at the reduced temperature level until said bistable means is set. 
     
     
       4. A solid state control circuit in accordance with claim 3 wherein said binary counter means includes a reset input, wherein said reference bias means also provides a second reference bias potential which is higher than the first reference bias potential, and wherein said automatic resetting means comprises a third comparator having a positive input coupled to said operating bias means such that the operating bias potential is coupled to said positive output, a negative input coupled to said reference bias circuit and biased by the second reference bias potential, and an output coupled to the reset input of said binary counter means, the operating bias potential increasing responsive to said temperature sensing means to exceed said second reference bias potential when said deep fat fryer is used before the predetermined time interval has elapsed and enabling said third comparator to develop a reset signal at said output for automatically resetting said counter means to initiate a new predetermined time interval. 
     
     
       5. A solid-state control circuit in accordance with claim 3 or 4 wherein said bistable means comprises a "D" flip/flop further having a clock input, a "D" input and a second output, said "D" input and said second output being interconnected such that said first output changes states between a low logic level state and a high logic level state responsive to pulses supplied to said clock input, and wherein said hold mode means includes means for manually switching said deep fat fryer between operation at the selected temperature and the reduced temperature of the hold mode, said manual hold mode switching means comprising normally open control switch means coupled to said DC power supply line and monostable multivibrator means coupled between said normally open control switch means and the clock input of said flip/flop, said monostable multivibrator providing a pulse to said flip/flop clock input responsive to manual closure of said control switch means to cause said first flip/flop output to change states, said first flip/flop output also being coupled to said oscillator means and said binary counter means to reset said oscillator means and said counter means to initiate a new predetermined time interval, said pulse from said monostable multivibrator causing said flip/flop to bias said first solid-state means off to unshort said one resistor and said second solid-state means on to short said operating temperature control means to switch said deep fat fryer to operation in the hold mode at the lower temperature level if said control switching means is manually depressed while said fryer is operating at the selected temperature level and said pulse causing said flip/flop to bias said first solid-state means on and said second solid-state means off if said control switch means is manually depressed while said fryer is operating in the hold mode at the reduced temperature level. 
     
     
       6. A solid-state control circuit in accordance with claim 5 including an indicator light, a triac coupled in series with said indicator light between said AC power lines and having a control input, and a transistor having an input coupled to the second output of said flip/flop and an output coupled to the control input of said triac, said flip/flop biasing said transistor to conduction to turn said triac on and connect said indicator light across said AC power lines when said fryer is being operated in the hold mode at the reduced temperature level, said indicator light thereupon lighting to give a visual indication that said fryer is operating at the reduced temperature level. 
     
     
       7. A solid-state control circuit in accordance with claim 3 including means selectively operable to switch said deep fat fryer to operation in a melt mode wherein said heating elements are cycled on and off to melt said cooking fat when said cooking fat is unmelted, said fat melt means comprising second bistable means having a clock input coupled to a first one of said counter means outputs, a reset input coupled to a second one of said counter means outputs, and an output, third solid-state means having an output coupled in parallel with said temperature sensing means and an input coupled to the output of said second bistable means, second melt control switch means coupled to said second bistable means for enabling operation in the fat melt mode and means coupled to said oscillator means and said binary counter means when said second bistable means is enabled, said second bistable means biasing said third solid-state means to conduction to short said temperature sensing means and couple said operating temperature control means to said reference power supply line when the first output of said counter means supplies a pulse to the clock input of said second bistable means at a first predetermined time interval after said oscillator means and said binary counter means are reset, said third solid-state means shorting said temperature sensing means during a subsequent second predetermined time interval to inhibit said first comparator from developing the enabling signal, said second counter means output providing a reset pulse to the reset input of said second bistable means after said second predetermined time interval to inhibit further pulses to the clock input of said second bistable means from turning said third solid-state means off during a subsequent third predetermined time interval, odd numbered ones of said clock pulses thereafter being effective to turn said third solid-state means off such that said first comparator generates the enabling signal and reset pulses subsequent to said odd numbered clock pulses causing said second bistable means to turn said third solid-state means on such that the enabling signal cannot be generated by said first comparator, said first comparator being allowed to cycle on for relatively short intervals to energize said heating elements and melt said cooking fat. 
     
     
       8. A solid-state control circuit in accordance with claim 7 wherein said first bistable means and said second bistable means have respective set inputs and wherein said second melt control switch means is coupled to said DC power supply line and operable to couple said second bistable means set input to said DC power supply line in a first switch position and said first bistable means to said DC power supply line in a second switch position, said second melt control switch being normally closed to the first switch position to disable said second bistable means and manually actuable to close to the second switch position to enable said second bistable means and initiate operation in the fat melt mode. 
     
     
       9. A solid-state control circuit in accordance with claim 8 including solid-state means for disabling said first comparator if said timing means fails, said solid-state disabling means having an output coupled in parallel with said temperature sensing means and having an input coupled to said DC power supply line through said second melt control switch means in the second fat melt switch position, a capacitor coupled to said input and having a discharge path comprising a diode coupled between said input and said third solid-state means coupled in parallel with said temperature sensing means, said capacitor being charged during intervals when said first comparator is developing the enabling signal and discharging through said diode and said third solid-state means during intervals when no enabling signal is being developed, said capacitor continuing to charge to bias said solid-state disabling means to conduction to short said temperature sensing means and inhibit said first comparator from developing the enabling signal if said timing means fails. 
     
     
       10. A solid-state control circuit in accordance with claim 8 including solid-state means for inhibiting reset pulses to said counter means during operation in the melt mode, said counter reset inhibiting means having an input coupled to said DC power supply line through said second melt control switch means when said second melt control switch means is closed to the second fat melt switch position and an output coupled the reset input of said binary counter means, said counter reset inhibiting means being biased to conduction to inhibit reset pulses to said counter means when said second melt control switch means is closed the second fat melt switch position. 
     
     
       11. A solid-state control circuit in accordance with claim 8 including solid-state means for inhibiting reset pulses to said second bistable means during operation in modes other than the melt mode, said second bistable reset inhibiting means having an input coupled the set input of said second bistable means and an output coupled to the reset input of said second bistable means, said second bistable reset inhibiting means being coupled to said DC power supply line through said second melt control switch means when said second melt control switch means is in the first switch position, said second bistable reset inhibiting means being biased to conduction to inhibit reset pulses to said second bistable means and disable said second bistable means when said deep fat fryer is not operating in the fat melt mode. 
     
     
       12. A solid-state control circuit in accordance with claim 8 including an indicator light, and wherein said second melt control switch means includes switch means coupled in series with said indicator light between said AC power lines, said switch means being ganged with said second melt control switch means to close when said second melt control switch means is manually switched to the first switch position and connect said indicator light across said AC power lines to provide a visual indication that said deep fat fryer is being operated in the fat melt diode.