Virtual addressing for I/O adapters

Abstract

In a paged, virtual memory computer system, apparatus is provided for enabling I/O adapters to use virtual addresses. After each I/O data transfer, the main memory address involved in the transfer is incremented. This address is maintained in an I/O register associated with the I/O adapter performing the transfer. If a page boundary is crossed in the process of incrementing, the channel forms an I/O event indicating the page crossing and calling for translation of the incremented address. When the I/O adapter involved in the page crossing attempts a further data transfer, the channel disconnects the I/O adapter. The channel holds the I/O adapter disconnected until the page crossing denoted by the I/O event has been resolved by translating the incremented address and providing a new main memory address for continuing the data transfer. Because the disconnect is effected by ignoring the priority of the disconnected adapter when it requests service, other adapters of lower priority can be serviced by the channel during the disconnect. When completion of the address translation is signalled, the I/O adapter is no longer held disconnected.

Having thus described the invention, what is claimed as new, and desired to be secured by Letters Patent is: 
     
       1. In a virtual memory computer system having a central processing unit, main memory and I/O adapters connected to the main memory by a channel, wherein said main memory has a plurality of addressable storage locations and a group of storage locations form a memory page having memory address boundaries, wherein both the CPU and the I/O adapters use virtual addressing and wherein the channel has a priority mechanism for granting use of the channel to the highest priority I/O adapter requesting use of the channel, the improvement comprising: an I/O address register for storing a memory address for addressing memory;   register means for storing memory addresses, where the register means is accessible by the channel and the CPU;   incrementing means for incrementing the memory address in the I/O address register;   detecting means for detecting when the incrementing means increments the memory address in the I/O address register to a value for addressing a memory location across a memory page boundary, said incremented memory address becoming invalid upon reaching the value for addressing a memory location across a memory page boundary;   means for translating an incremented memory address in said I/O address register which crosses a page boundary into a valid main memory address and for providing a translation completion signal to the channel upon completion of the address translation; and   disconnection means in the channel for disconnecting an I/O adapter from the channel when the I/O adapter requests use of the channel and the I/O address register after the detecting means has detected that a memory address in the I/O address register has crossed a page boundary, said disconnection means holding said I/O adapter disconnected when said I/O adapter requests use of the channel and the I/O address register until the channel receives the translation completion signal indicating completion of address translation, said disconnection means otherwise permitting the I/O adapter to request and use the channel via said register means and provided use of the I/O address register is not requested.   
     
     
       2. The system as recited in claim 1 further comprising invalid address indicating means associated with the I/O address register and in communication with the disconnection means for indicating that the memory address in the I/O address register has crossed a page boundary and that translation of the incremented address has not been completed. 
     
     
       3. The system as recited in claim 2 wherein the invalid address indicating means comprises a valid page field in the I/O address register. 
     
     
       4. The system as recited in claim 3 wherein the means for translating an incremented memory address and for providing a signal upon completion of translation comprises means for setting the valid page field in the I/O address register. 
     
     
       5. The system as recited in claim 4 wherein the disconnection means comprises means for testing the valid page field in the I/O address register to determine whether or not the memory address in the I/O address register has crossed a page boundary and translation of the incremented address has been completed. 
     
     
       6. The system as recited in claim 1 wherein the disconnection means comprises means connected to the priority mechanism for causing the priority of an I/O adapter requesting use of the channel to be ignored when a page boundary crossing in the memory address in the I/O address register has been detected by the detecting means during a previous use of the channel by that I/O adapter and translation of the incremented address has not been completed. 
     
     
       7. The system as described in claim 1 wherein the means for translating an incremented I/O address and for providing a signal upon completion of translation comprises means for placing the valid translated address into the I/O address register.