Self-aligned contacts in an ion implanted VLSI circuit

Abstract

A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.

I claim: 
     
       1. A process for forming very large scale integrated circuits on a monocrystalline silicon semiconductor substrate comprising the steps of thermally growing a first silicon dioxide layer on a first surface of said silicon semiconductor substrate, selectively applying a first silicon nitride layer on said first silicon dioxide layer, said first silicon nitride layer being applied at least in a first selected area in which a field effect semiconductor device is to be formed and in at least a second selected area in which a diffused conducting line is to be formed,   thermally oxidizing said silicon semiconductor substrate whereby thick field oxide regions are grown surrounding said first and second selected areas whereby said first silicon nitride layer substantially prevents the growth of additional silicon dioxide regions in said portions of said silicon substrate thereunder and whereby said thermal oxidation forms a thin silicon oxynitride layer on the surface of said first silicon nitride layer,   forming a polysilicon layer on the surface of said silicon oxynitride layer and said field oxide region, said polysilicon layer extending over said selected areas,   forming a second silicon dioxide layer on top of said polysilicon layer,   selectively applying a silicon nitride stripe on said second silicon dioxide layer juxtaposed on one of said field oxide regions,   selectively removing portions of said second silicon dioxide layer and said polysilicon layer to define a polysilicon gate electrode extending transversely and centrally of said selective area for said active device and to define a polysilicon line traversing at least one of said field regions, the surface of said polysilicon layer covered by portions of said second silicon dioxide layer and said silicon nitride stripe, said polysilicon line having a width greater than that of said silicon nitride stripe in the area immediately surrounding said silicon nitride stripe,   oxidizing said polysilicon gate electrode and line, covered with said second silicon dioxide layer, to form a thick third silicon dioxide layer thereon, whereby said first silicon nitride layer and said silicon nitride button substantially prevent the formation of silicon dioxide thereunder,   selectively removing portions of said first silicon nitride layer and said silicon stripe, wherein the remaining portions thereof define areas on the surface of said silicon semiconductor substrate to become the source and drain contacts of said field effect device, the polysilicon line contact and the diffused line contact,   thermally oxidizing the surface of the diffused line and the polysilicon line, whereby said first silicon nitride layer and said silicon nitride stripe protect the polysilicon layer and the silicon semiconductor substrate thereunder from substantially forming a silicon dioxide layer,   batch removing in sequence the exposed silicon oxynitride, silicon nitride, and silicon oxide layers, whereby said source and drain contacts, polysilicon line contact, and diffused line contact are exposed,   providing electrical interconnections to said source and drain contacts, polysilicon line contact, and diffused line contact.   
     
     
       2. A process as in claim 1, further comprising the step of: implanting dopant ions into the surface of said silicon semiconductor substrate at least in said first and second selected areas by means of an ion implanter, whereby said thick field oxide regions and said thick third silicon dioxide layer prevent the implantation of dopant ions into the surface of said silicon semiconductor substrate thereunder, said implanting step performed after said step of oxidizing said polysilicon electrode and line.   
     
     
       3. A process as in claim 1 or 2, wherein said step of forming a polysilicon layer comprises forming a polysilicon layer including dopant ions therein. 
     
     
       4. A process as in claim 1, wherein said steps of selectively removing respectively, silicon dioxide and silicon nitride portions comprise the steps of: applying a layer of photoresist, exposing said photoresist layer to actinic radiation through a mask having protective regions thereon, said protective regions opaque to said actinic radiation,   applying a developer to said photoresist layer to dissolve regions thereof, whereby said photoresist layer regions not exposed to said actinic radiation have a substantially different solubility than those regions of said photoresist layer exposed to actinic radiation,   and respectively etching said exposed silicon dioxide and silicon nitride portions, wherein said etching process respectively removes silicon dioxide and silicon nitride without substantially affecting said undissolved photoresist regions, whereby said respective silicon dioxide and silicon nitride juxtaposed under said undissolved photoresist are substantially unaffected by said etching process.   
     
     
       5. A process as in claim 4, wherein said step of selectively applying silicon nitride comprises: applying a layer of silicon nitride,   selectively removing a portion of said silicon nitride layer.   
     
     
       6. A process for forming very large scale integrated circuits on a monocrystalline silicon semiconductor substrate having field oxide regions surrounding and isolating at least a first selected area in which a field effect semiconductor device is to be formed and at least a second selected area in which a diffused conducting line is to be formed and having polysilicon line conductors disposed on said field oxide and for providing self-aligned contacts to at least selected ones of said conductors comprising the steps of: thermally growing a first silicon dioxide layer on each of said first and second selected areas,   forming a silicon nitride layer on said first silicon dioxide layer,   forming a silicon oxynitride layer on said first silicon nitride layer,   forming a polysilicon layer on said silicon oxynitride layer extending over said selected areas and said field oxide region,   forming a protective button on said polysilicon layer, juxtaposed over the location of a corresponding said polysilicon line conductor to be formed, and of lesser width than said line,   defining a polysilicon gate electrode extending transversely and centrally of said selected area for said active device, and a polysilicon line conductor, extending at least in part over said field region, of greater width dimension than said button and intersecting same in an intersection region, to be formed from said polysilicon layer,   delineating said polysilicon layer to form said line conductor with said conformed button juxtaposed thereon and to form said gate electrode,   protecting the portions of said first silicon oxynitride and nitride layers on said source and drain regions and on a selected contact area of said diffused conducting line and removing all unprotected portions of said first silicon oxynitride and silicon nitride layers,   removing the silicon dioxide layer portions exposed by removal of said first silicon nitride layer portions,   forming a thermal oxide on exposed surfaces of said gate polysilicon layer, of said polysilicon line conductor, and of said diffused line, and   removing said first silicon oxynitride and nitride layers from said source and drain regions and said diffused conducting line and removing said button, thereby to expose said contact surfaces of said source and drain regions, of said diffused conducting line and of said polysilicon line conductor.   
     
     
       7. A process as recited in claim 6, further comprising a step of providing conductor lines on said semiconductor substrate extending over said field oxide and onto said polysilicon line contact for providing electrical connection thereto. 
     
     
       8. A process as recited in claim 6, wherein said button comprises a silicon nitride layer, and said step of removing said button comprises applying a material to said substrate which selectively removes nitride and has no substantial effect on said insulating thermal oxide. 
     
     
       9. A process as in claim 6, further comprising the step of simultaneously doping said source, drain, and diffused conducting line regions with an ion implant doping means. 
     
     
       10. A process for forming very large scale integrated circuits on a monocrystalline silicon semiconductor substrate having field oxide regions surrounding and isolating at least a first selected area in which a field effect semiconductor device is to be formed and at least a second selected area in which a diffused conducting line is to be formed and having polysilicon line conductors disposed on said field oxide and for providing self-aligned contacts to at least selected ones of said conductors comprising the steps of: thermally growing a first silicon dioxide layer on each of said first and second selected areas,   forming a first silicon nitride layer on said first silicon dioxide layer, forming a silicon oxynitride layer on said first silicon nitride layer,   forming a polysilicon layer on said silicon oxynitride layer extending over said selected areas of said field oxide region,   forming a second silicon nitride layer on said polysilicon layer,   retaining a selected portion of said second silicon nitride layers overlying said field region as a button having a width dimension smaller than the width of a polysilicon line conductor to be formed from said polysilicon layer on said field region and removing remaining portions of said second silicon oxynitride and silicon nitride layers,   defining a polysilicon gate electrode, extending transversly and centrally of said selected area for said active device, and a polysilicon line conductor, extending at least in part over said field region, of greater width dimension than said button and intersecting same in an intersection region, to be formed from said polysilicon layer,   delineating said polysilicon layer to form said line conductor with said button juxtaposed thereon and to form said gate electrode,   protecting the portions of said first silicon oxynitride and nitride layers on said source and drain regions and on a selected contact area of said diffused conducting line and removing all unprotected portions of said first silicon oxynitride and silicon nitride layers,   removing the silicon dioxide layer portions exposed by removal of said first nitride layer portions,   forming a thermal oxide on exposed surfaces of said gate polysilicon layer, of said polysilicon line conductor, and of said diffused line, and, in sequence,   removing exposed portions of said first oxynitride layer and the thereby exposed portions of said first and second nitride layers,   removing the exposed portions of said silicon dioxide layer exposed by removal of said portions of said first silicon nitride layer and any oxide on the exposed contact surface of said polysilicon line conductor, thereby to expose said contact surfaces of said source and drain regions, of said diffused conducting line, and of said polysilicon line conductor.   
     
     
       11. A process as recited in claim 10, further comprising the step of: prior to the step of protecting the portions of said first silicon oxynitride and nitride layers, simultaneously doping all of said source and drain regions, and said diffused conducting line by ion implant doping.   
     
     
       12. A process for fabricating a field effect semiconductor device having source, drain, and gate regions on a selected area of a first surface of a monocrystalline silicon substrate comprising the steps of: thermally growing a silicon dioxide layer on said selected area of said first surface of a thickness suitable for the gate insulator layer of said field effect device,   forming a first silicon nitride layer on said silicon dioxide layer,   forming a first silicon oxynitride layer on said first silicon nitride layer,   forming a polysilicon layer on said first silicon oxynitride layer,   forming a second silicon nitride layer on said polysilicon layer,   removing said second nitride layer except for retaining a gate contact surface defining portion thereof extending transversly of said selected area in the region of a gate to be defined,   protecting said retained portion of said second silicon nitride layer while delineating said polysilicon layer to define a gate polysilicon layer electrode extending transversly of said selected area of said active device of lesser width than and in alignment with said retained portion of said second silicon nitride layer, said gate polysilicon layer electrode defining first and second remaining portions of said selected area corresponding to source and drain regions of said device,   thermally oxidizing the surface of said gate polysilicon layer electrode while retaining said first silicon nitride and silicon oxynitride layers over said source and drain regions of said active device to prevent formation of any substantial amount of oxide thereon,   removing the portions of said first silicon oxynitride layer from said source and drain regions,   removing said retained second nitride layer portion from said gate polysilicon layer electrode and simultaneously removing the portions of said first nitride layer portions from said source and drain regions, and   removing any silicon dioxide from said gate polysilicon electrode exposed by removal of said second silicon nitride and silicon oxynitride layer portions therefrom, to expose the underlying contact surface of said gate polysilicon layer electrode defined thereby, and simultaneously removing said silicon dioxide layer from said source and drain region sources, thereby to provide a direct contact to said gate polysilicon layer electrode.   
     
     
       13. A process for fabricating a field effect semiconductor device having source, drain, and gate regions on a selected area of a first surface of a monocrystalline silicon substrate comprising the steps of: thermally growing a silicon dioxide layer on said selected area of said first surface of a thickness suitable for the gate insulator layer of said field effect device,   forming a first silicon nitride layer on said silicon dioxide layer,   forming a first silicon oxynitride layer on said first silicon nitride layer,   forming a polysilicon layer on said first silicon oxynitride layer,   forming a protection layer on said polysilicon layer, said protection layer being substantially non-oxidizable by thermal oxidation and being removable by a material-selective removal process having no substantial effect on silicon and silicon dioxide surfaces,   removing said protection layer except for retaining a gate contact surface defining portion thereof extending transversly of said selected area in the region of a gate to be defined,   protecting said retained portion of said protection layer while delineating said polysilicon layer to define a gate polysilicon layer electrode extending transversly of said selected area of said active device of lesser width than and in alignment with said retained portion of said protection layer, said gate polysilicon layer electrode defining first and second remaining portions of said selected area corresponding to source and drain regions of said device,   thermally oxidizing the surface of said gate polysilicon layer electrode while retaining said first silicon nitride and silicon oxynitride layers over said source and drain regions of said active device to prevent formation of any substantial amount of oxide thereon,   removing said retained, protection layer portion from said gate polysilicon layer electrode and removing said first silicon oxynitride and silicon nitride layers from said source and drain regions, and   removing any silicon dioxide from said gate polysilicon electrode exposed by removal of said protection layer portion therefrom, to expose the underlying contact surface of said gate polysilicon layer electrode defined by said protection layer portion, and simultaneously removing said silicon dioxide layer from said source and drain region sources, thereby to provide a direct contact to said gate polysilicon layer electrode.   
     
     
       14. A process as recited in claim 13 wherein said protection layer comprises a layer of silicon nitride. 
     
     
       15. A process for forming very large scale integrated circuits on a monocrystalline silicon semiconductor substrate having field oxide surrounding and isolating at least one selected area in which a field effect semiconductor device is to be formed and having at least one polysilicon line conductor disposed at least in part on said field oxide and for providing self-aligned contacts to at least the source and drain regions of said device and to said polysilicon line conductor at a selected location thereof, comprising the steps of: thermally oxidizing the surface of said semiconductor substrate in said selected area to form a first silicon dioxide layer thereon,   forming a first silicon nitride layer on said first silicon dioxide layer,   forming a first silicon oxynitride layer on said first silicon nitride layer,   forming a layer of polysilicon on said first silicon oxynitride layer and on said field oxide,   forming a protective button on said polysilicon layer, juxtaposed over the location of the corresponding said polysilicon line conductor to be formed, and of lesser width and said line conductor,   defining a polysilicon line conductor to be formed from said polysilicon layer in accordance with the said juxtaposed position of said button and defining a polysilicon gate electrode to be formed in said polysilicon layer, said gate electrode extending transversely and centrally of said selected area for said active device,   delineating said polysilicon layer to provide said polysilicon line conductor and said polysilicon gate electrode,   thermally oxidizing said polysilicon line conductor and said polysilicon gate electrode to form an insulating oxide on exposed surfaces thereof while said button prevents thermal oxidation of the line portion on which it is juxtaposed and said first silicon nitride and oxynitride layer prevent thermal oxidation of said source and drain regions,   removing said button and said first silicon oxynitride and nitride layers overlying said source and drain regions of said device,   removing the silicon dioxide layer portions exposed by removal of said first silicon oxynitride and nitride layers and removing any oxide on the surface of said polysilicon line conductor exposed by removal of said button, thereby to expose said contact surfaces of said source and drain regions and of said diffused conducting line.   
     
     
       16. A process as recited in claim 15, further comprising a step of providing conductor lines on said semiconductor substrate extending over said field oxide and onto said polysilicon line contact for providing electrical connection thereto. 
     
     
       17. A process as recited in claim 15, wherein said button comprises a silicon nitride layer, and said step of removing said button comprises applying a material to said substrate which selectively removes nitride and has no substantial affect on said insulating thermal oxide. 
     
     
       18. A process as in claims 6, 10, 12, 13, or 15, wherein said step of forming a layer of polysilicon comprises forming a layer of polysilicon having dopant ions therein. 
     
     
       19. A very large scale integrated circuit produced in accordance with the process of claims 1, 6, 10, or 15. 
     
     
       20. A field effect semiconductor device produced in accordance with the process of claims 12 or 13.