Circuit arrangement for an indirectly controlled exchange, in particular a telephone exchange

Abstract

A circuit arrangement for an indirectly controlled exchange, in particular a telephone exchange, is provided with central control devices and, on the occurrence of a fault signal, for the retention of the operating states currently prevailing in the exchange, items of test data concerning the electrical states at specific test points are input into a memory, for which purpose the operating state prevailing in the exchange is temporarily maintained. The circuit arrangement includes two parallel operating control devices, each of which has a data bus and is additionally equipped with a status memory which serves to accommodate test data. The status memory includes an input which is connected to the respective data bus and an output which is connected to the data bus of the other control device. Each status memory is connected to at least one device which supplies fault signals and also to terminals which supply control signals of the control devices. As a result of a control signal which follows a fault signal the entire test data contained in the two status memories is transferred into two working memories of the two control devices. In each of the two control devices test data corresponding to one another are compared and the test data, together with the comparison results are fed, for further analysis, from each control device to its output device.

We claim: 
     
       1. A circuit arrangement for an indirectly-controlled exchange, in particular a telephone exchange, which is provided with central control devices and in which, upon the occurrence of a fault signal, the operating status of the exchange is temporarily maintained and items of data concerning the electrical states prevailing at test points are input into a memory in order to retain the currently prevailing operating states, comprising first and second parallel-operating control devices, said control devices including first and second working memories, respectively,   first and second data buses, respectively,   first and second status memories, respectively, each including an input connected to its respective data bus and an output connected to the opposite respective data bus,     at least one fault device operable to supply fault signals connected to each of said data buses,   first and second terminals for receiving control signals connected to said data buses,   transfer means operable in response to a control signal which follows a fault signal to transfer the test data stored in said status memories into said working memories,   first and second output devices, and   comparison means for comparing the test data of the two control devices and feeding the test data and the comparison results to said output device.   
     
     
       2. The circuit arrangement of claim 1, wherein said first and second control devices comprise: first and second flow control devices, respectively, connected to said fault device and to said transfer means and operable to provide a control signal to cause the transfer of data.   
     
     
       3. The circuit arrangement of claim 2, wherein: said fault device comprises a comparator including inputs connected to said first and second data buses and outputs connected to said flow control devices and to said status memories.   
     
     
       4. The circuit arrangement of claim 1, comprising: means for supplying a control signal after an interruption of the processing of a machine command by a fault signal.   
     
     
       5. The circuit arrangement of claim 1, wherein: said first and second output devices each comprise data printers.   
     
     
       6. The circuit arrangement of claim 1, comprising: at least one parity checking device as said fault device for checking the data occurring in a control device.   
     
     
       7. The circuit arrangement of claim 1, wherein: said fault device comprises a time-measuring device for monitoring the flow of time-limited processes and operable to provide a fault signal in response to an impermissible delay of one process by another.   
     
     
       8. The circuit arrangement of claim 1, comprising: first and second flow control devices respectively in said first and second control devices connected to said fault device and to said transfer means and operable to provide a control signal to cause the transfer of data, said flow control devices also operable to handle machine commands the execution of which must be handled by the various components of the control devices, and including test command means operable in response to a first machine command and in the absence of a second machine command to carry out a test command to cause the transfer of data from said status memories to said working memories.   
     
     
       9. The circuit arrangement of claim 8, wherein: said test command means includes means for producing a test command which identifies the data to be compared by said fault device.   
     
     
       10. The circuit arrangement of claim 8, comprising: switching means operated by one of said flow control devices to interconnect said first and second data buses so that items of data which correspond to each other and which occur during handling of a machine command may be compared in order to discover faults.   
     
     
       11. The circuit arrangement of claim 8, wherein: each of said control devices comprises a plurality of control sub-devices connected to the respective data bus, and a respective address bus connecting the respective control sub-devices and status memory to the respective flow control device, and   each of said status memories comprises an input control device connected to its respective data and address buses, and an output control device connected to each of the mentioned address and data buses,   said flow control devices supplying addresses to consecutively access said control sub-devices and input data therefrom into said status memories via said input control devices and to output data via said output control devices and input the same, via said data buses, into said working memories.