US4190900AExpiredUtility
Major/minor loop bubble memory with timing loop
Est. expiryMar 27, 1998(expired)· nominal 20-yr term from priority
Inventors:David Curtis Van Voorhis
G11C 19/0875
31
PatentIndex Score
0
Cited by
2
References
6
Claims
Abstract
A major/minor loop bubble memory configuration that provides gap free serial access to the data in the minor loops and which maintains the non-volatility of data when subjected to a power-on-off-on sequence. The configuration includes a timing minor loop in combination with the data storage minor loops in the major/minor loop array. The placement of a single timing bubble within the timing loop permits gap free serial access to the data in the remaining storage minor loops.
Claims
exact text as granted — not AI-modifiedI claim:
1. A bubble domain memory system having a major/minor loop array suitable for the storage and guided movement of bubble domains, the system comprising; a plurality of minor loops in said array adapted for the storage of data encoded as the presence or absence of bubble domains, a major loop positioned adjacent to the minor loops, said major loop including sensing means for detecting the presence or absence of bubbles, and a minor loop having a single bubble therein adapted for timing purposes and positioned adjacent to said major loop and closer to said sensing means than said data storage minor loops, and said timing minor loop adapted for retaining the rotational position of bubble domains in said data storage minor loops to provide gap-free serial access to the stored data.
2. A bubble domain system as described in claim 1 having M data loops, and said data loops having N bits of data, where N is an odd number.
3. A bubble domain system as described in claim 2 wherein 2M and N are relatively prime.
4. A bubble domain system as described in claim 2 wherein 2M+2 and N are relatively prime.
5. A bubble domain memory system having a major/minor loop array suitable for the storage and guided movement of bubble domains, the system comprising a major loop having a write portion channel and a read portion channel, a first data switch for transferring data into said write portion channel, a plurality of minor loops in said array adapted for the storage of data as the presence or absence or bubble domains, said minor loops having a first end associated with said write channel and a second end associated with said read channel, said plurality of minor loops including a first data loop positioned at the top of said array, a second data switch for transferring data from said write portion channel into said first data loop, a minor loop having a single bubble therein adapted for timing purposes and positioned below said data storage minor loops and at the bottom of said array, a third switch in said timing minor loop for transferring the timing bubble into said read portion channel, and a sensing element connected to said read portion channel for detecting the presence or absence of bubbles.
6. A bubble domain system as described in claim 5 wherein LD+SL+2M=(N-1)/2 where LD is the number of bit positions in said read portion channel between said third switch and said sensing element, SL is the number of bit positions in said write portion channel between said first data switch and said second data switch, M is the number of data storage minor loops, and N is the number of bit positions in the data storage minor loops.Join the waitlist — get patent alerts
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