Transistor power amplifier for transmitting systems

Abstract

A transistor power amplifier for transmitting systems, particularly high frequency systems, has two parallel connected signal paths each of which is fed with the input signal. In a first of the signal paths, a 6 dB attenuator connects the input to the input of an amplifier and a fraction of the output of the amplifier is connected to one input of a correction amplifier, constructed as a differential amplifier. In the other signal path a delay member which simulates the delay of the first amplifier connects the circuit input to another input of the correction amplifier. The correction amplifier therefore is provided with a fraction of a delayed amplified signal which is subjected to error and includes an error component and with the delayed original input signal and emits a control signal for a second amplifier in which the error component produced in the first amplifier is contained in a double and inverted magnitude. A parallel connection of this signal with the delayed original input signal, further attenuated by 3 dB, is provided to the second amplifier which is in the second signal path. A second delay member is connected to the output of the first amplifier to simulate the delay of the second amplifier, and the second delay member and the output of the second amplifier are provided in a parallel connection to produce the output of the transistor power amplifier.

I claim: 
     
       1. A transistor power amplifier for transmission systems, particularly in the short-wave range, comprising: a power amplifier input, a power amplifier output, and first and second parallel-connected signal paths extending between said power amplifier input and said power amplifier output;   first amplifier means in said first signal path including an input coupled to said power amplifier input and an output, and having a first predetermined delay time and operable to subject input signals to an error;   second amplifier means in said second signal path including an input and an output and having a second predetermined delay time;   first delay means in said second signal path including an input coupled to said power amplifier input and an output, and operable to simulate said first predetermined delay time;   second delay means in said first signal path including an input connected to said output of said first amplifier means and an output, an operable to simulate said second predetermined delay time;   output means connecting said output of said second delay means and said output of said second amplifier means to said power amplifier output;   signal branching means connected to said output of said first amplifier means for providing a portion of the output signal of said first amplifier means;   correction amplifier means comprising a differential amplifier including first and second inputs and an output, said first input connected to said output of said first delay means, said second input connected to said signal branching means, and said differential amplifier operable to provide a correction signal which includes the error component produced in said first amplifier means inverted and of twice the magnitude thereof; and   signal combining means coupling said output of said first delay means and said output of said differential amplifier to said input of said second amplifier means, comprising a transformer including a primary winding coupled to said output of said first delay means and to said output of said differential amplifier and a secondary winding connected to said input of said second amplifier means.   
     
     
       2. The transistor power amplifier of claim 1, wherein said first and second amplifier means are identically constructed, and further comprising a first attenuator serially interposed between said power amplifier input and said input of said first amplifier means, and a second attenuator serially interposed between said output of said first delay means and said primary winding of said transformer. 
     
     
       3. The transistor power amplifier of claim 2, wherein the attenuator in said first signal path is a 6 dB attenuator and the attenuator in said second signal path is a 3 dB attenuator.