Arrangement for testing telecommunication repeaters

Abstract

A repeater connected in a telecommunication line receiving a pseudorandom digital signal from the line is tested in-line by superimposing a noise signal of steadily increasing amplitude on the digital signal and measuring the amplitude of the noise signal at an output of the source of the noise signal when the amplitude of the noise signals produces a predetermined number of errors in the digital signal at the output of the repeater.

I claim: 
     
       1. An arrangement for in-line testing of a telecommunication repeater of the digital regenerator type comprising: a transmission line for transmitting a digital signal;   a repeater under test coupled into said transmission line to regenerate said digital signal;   a noise generator to generate a noise signal of steadily increasing amplitude;   an impedance transformer coupled to said noise generator and the input of said repeater to superimpose said noise signal on said digital signal;   an error detector coupled to the output of said repeater to produce an error output signal when the amplitude of said noise signal has increased until errors are produced in said digital signal at the output of said repeater; and   first means coupled to the output of said error detector and said noise generator, said first means being responsive to said error output signal for sampling and measuring the voltage amplitude of a signal in said noise generator and to reset said noise generator to zero.   
     
     
       2. An arrangement according to claim 1, wherein said noise generator includes an oscillator,   a ramp generator, and   a modulator coupled to said oscillator and said ramp generator to modulate an output signal from said oscillator by a ramp waveform at the output of said ramp generator.     
     
     
       3. An arrangement according to claim 2, wherein said oscillator produces a sine wave signal,   said ramp generator generates a comparatively low frequency ramp waveform, and   said modulator modulates said sine wave signal by said low frequency ramp waveform.   
     
     
       4. An arrangement according to claim 3, wherein said first means is coupled to said ramp generator to sample and measure the voltage amplitude of said low frequency ramp waveform and to reset said ramp generator to zero.   
     
     
       5. An arrangement according to claim 4, wherein said first means includes a sample and hold circuit coupled to the output of said error detector and an output of said ramp generator,   a meter coupled to said sample and hold circuit to indicate the voltage amplitude of said low frequency ramp waveform which produced said error output signal, and   a time delay circuit coupled to the output of said error detector and said ramp generator to delay the resetting of said ramp generator a predetermined length of time after said error output signal is produced.     
     
     
       6. An arrangement according to claim 5, wherein said error detector includes a second means coupled to the output of said repeater to divide the output signal of said repeater into a first stream of positive pulses and a second stream,   third means coupled to said second means to measure the disparity between said first and second streams, and   an up-down counter coupled to said third means to accumulate the total number of disparities.     
     
     
       7. An arrangement according to claim 6, wherein said digital signal is a 4B3T code having a maximum disparity of four, and   said up-down counter is a four bit up-down counter which generates said error output signal when five disparities are accumulated.   
     
     
       8. An arrangement according to claim 2, wherein said first means is coupled to said ramp generator to sample and measure the voltage amplitude of a ramp waveform and to reset said ramp generator to zero.   
     
     
       9. An arrangement according to claim 8, wherein said first means includes a sample and hold circuit coupled to the output of said error detector and an output of said ramp generator,   a meter coupled to said sample and hold circuit to indicate the voltage amplitude of a ramp waveform which produced said error output signal, and   a time delay circuit coupled to the output of said error detector and said ramp generator to delay the resetting of said ramp generator a predetermined length of time after said error output signal is produced.     
     
     
       10. An arrangement according to claim 9, wherein said error detector includes a second means coupled to the output of said repeater to divide the output signal of said repeater into a first stream of positive pulses and a second stream,   third means coupled to said second means to measure the disparity between said first and second streams, and   an up-down counter coupled to said third means to accumulate the total number of disparities.     
     
     
       11. An arrangement according to claim 10, wherein said digital signal is a 4B3T code having a maximum disparity of four, and   said up-down counter is a four bit up-down counter which generates said error output signal when five disparities are accumulated.   
     
     
       12. An arrangement according to claim 1, wherein said first means includes a sample and hold circuit coupled to the output of said error detector and said noise generator,   a meter coupled to said sample and hold circuit to indicate the voltage amplitude of a signal in said noise generator when said error output signal is produced, and   a time delay circuit coupled to the output of said error detector and said noise generator to delay the resetting of said noise generator a predetermined length of time after said error output signal is produced.     
     
     
       13. An arrangement according to claim 12, wherein 
     
     
       said error detector includes a second means coupled to the output of said repeater to divide the output signal of said repeater into a first stream of positive pulses and a second stream,   third means coupled to said second means to measure the disparity between said first and second streams, and   an up-down counter coupled to said third means to accumulate the total number of disparities.   
     
     
       14. An arrangement according to claim 13, wherein said digital signal is a 4B3T code having a maximum disparity of four, and   said up-down counter is a four bit up-down counter which generates said error output signal when five disparities are accumulated.   
     
     
       15. An arrangement according to claim 1, wherein said error detector includes a second means coupled to the output of said repeater to divide the output signal of said repeater into a first stream of positive pulses and a second stream,   third means coupled to said second means to measure the disparity between said first and second streams, and   an up-down counter coupled to said third means to accumulate the total number of disparities.     
     
     
       16. An arrangement according to claim 15, wherein said digital signal is a 4B3T code having a maximum disparity of four, and   said up-down counter is a four bit up-down counter which generates said error output signal when five disparities are accumulated.   
     
     
       17. A method of in-line testing of a telecommunication repeater of the digital regenerator type comprising the steps of feeding a pseudo-random digital signal to said repeater input from a telecommunication line;   superimposing a noise signal of steadily increasing amplitude on said digital signal, said noise signal being provided by a noise signal source; and   measuring the amplitude of said noise signal at an output of said source when the amplitude of said noise signal produces a predetermined number of errors in said digital signal at the output of said repeater.   
     
     
       18. A method according to claim 17, further including the step of adjusting said repeater to obtain a condition in which said repeater will operate at its optimum in a noisy environment.