Method for forming electrically-isolated regions in integrated circuits utilizing selective epitaxial growth

Abstract

An improved process for forming electrically-isolated regions in integrated circuits in the form of dielectric moats surrounding the regions and P-N junctions underlying the regions. Moats or notches are etched into the substrate prior to the formation of the buried isolation layer or further device information. A dielectric material such as silicon dioxide is deposited in the notches or moats and polycrystalline silicon is thereafter grown on the surface of the wafer to fill the notches or moats. The excess polysilicon formed on the surface of the wafer is then removed by mechanical lapping or polishing. Since there has been no doping or epitaxial growth, the wafer may be lapped directly to the substrate to remove all of the polysilicon and oxide from the surface while leaving the notches or moats lined with dielectric material and filled with polysilicon. There is thus no criticality to the lapping operation.

What is claimed is: 
     
       1. A method for forming electrically-isolated regions in a semiconductor substrate of a first conductivity type comprising the steps of first, etching notches in said substrate surrounding said isolated regions, second, depositing a silicon dioxide layer on the surface of said substrate, third, growing polycrystalline silicon on the surface of said substrate to fill said notches, fourth, lapping substantially to the surface of said substrate to re-expose said substrate at said isolated regions, fifth, forming isolation junctions of opposite conductivity type in said substrate at said isolated regions, sixth, forming dielectric mesas on said notches, and seventh, selectively growing an epitaxial layer of said opposite conductivity type on the surface of said substrate only at said isolated regions between said mesas. 
     
     
       2. The method according to claim 1 wherein said substrate is oriented in the 1-0-0 crystal orientation. 
     
     
       3. The method according to claim 1 wherein the step of forming isolating junctions comprises forming a mask on the surface of said substrate having apertures defining said isolated regions and doping the surface of said substrate through the apertures in said mask to the conductivity-type opposite the conductivity-type of the substrate. 
     
     
       4. The method according to claim 1 wherein the thickness of said dielectric mesas substantially corresponds to the thickness of said epitaxial layer. 
     
     
       5. The method according to claim 1 wherein the step of forming dielectric mesas comprising successively depositing layers of silicon dioxide, polycrystalline silicon and silicon dioxide on the surface of said substrate and selectively etching said layers to re-expose the surface of said substrate at said isolated regions. 
     
     
       6. The method according to claim 1 wherein said step of selectivity growing an epitaxial layer comprises disposing said wafer in an epitaxial reactor, purging said reactor with nitrogen, then purging said rector with hydrogen, then treating the surface of said wafer with HCl etchant and thereafter introducing a suitable mixture of hydrogen, silicon tetrachloride and dopant material to achieve epitaxial deposition at a rate of about 0.8 microns per minute. 
     
     
       7. The method according to claim 1 wherein said semiconductor devices are bipolar transistors.