Minipowered optional self checking electronic timer for ordnance

Abstract

A digital system is disclosed for providing long time delays. The system ludes two interconnected circulating shift registers which are particularly suited for fabrication by integrated circuit techniques. Additional elements in the system are also disclosed for adapting the digital timer for ordnance applications.

What is claimed is: 
     
       1. A time delay circuit including: a first shift register having an input and an output;   a second shift register having an input and an output;   means for connecting said input of said first shift register to said output thereof;   a full binary adder having first, second and third inputs, a sum output and a carry output;   means for connecting said output of said second shift register to said first input of said full binary adder;   means for connecting said sum output to said input of said second shift register;   means for connecting said output of said first shift register to said second input of said full binary adder;   delay means for connecting said carry output to said third input of said binary full adder;   an "And" gate having first and second inputs;   means for connecting said output of said first shift register to said first input of said "And" gate; and   means for connecting said third input of said binary full adder to said second input of said "And" gate.   
     
     
       2. The time delay circuit as defined in claim 1 in which said first and second shift registers have an equal number of stages. 
     
     
       3. The time delay circuit as defined in claim 2 in which information in said first and second shift registers are advanced at a predetermined bit interval; and said delay means is one bit interval long. 
     
     
       4. The time delay circuit as defined in claim 1 also including: means for inserting a "1" in one stage of said first shift register.   
     
     
       5. The time delay circuit as defined in claim 4 also including: a preset capability; and   means for remotely supplying a coded signal to the input of the second shift register.   
     
     
       6. The time delay circuit as defined in claim 5 also including: a third "And" gate having first and second inputs;   means for connecting said output of said first shift register to said first input of said third "And" gate; and   means for connecting said sum output of said full binary adder to said second input of said third "And" gate;   a delay flip flop having an input and an output;   means for connecting said output of said third "And" gate to said input of said delay flip flop;   an "exclusive-or" gate having first and second inputs;   means for connecting said sum output of said full binary adder to first input of said "exclusive-or" gate; and means for connecting said output of said delay flip flop to said second input of said "exclusive-or" gate;   a fourth "And" gate having first and second inputs;   means for connecting said output of said "exclusive-or" gate to said first input of said fourth "And" gate; and means for connecting said output of said first shift register to said second input of said fourth "And" gate.   
     
     
       7. The time delay circuit as defined in claim 1 also including: a second "And" gate having first and second inputs;   means for connecting said third input of said binary full adder to said first input of said second "And" gate; and   means for connecting an intermediate stage of said first shift register to said second input of said second "And" gate.   
     
     
       8. The time delay circuit as defined in claim 7 also including: an output flip flop; and   means for selectively connecting said first and second "And" gates to said flip flop.   
     
     
       9. The time delay circuit as defined in claim 8 also including: a third "And" gate having first and second inputs;   means for connecting said output of said first shift register to said first input of said third "And" gate; and   means for connecting said sum output of said full binary adder to said second input of said third "And" gate;   a delay flip flop having an input and an output;   means for connecting said output of said third "And" gate to said input of said delay flip flop;   an "exclusive-or" gate having first and second inputs;   means for connecting said sum output of said full binary adder to first input of said "exclusive-or" gate; and means for connecting said output of said delay flip flop to said second input of said "exclusive-or" gate;   a fourth "And" gate having first and second inputs;   means for connecting said output of said "exclusive-or" gate to said first input of said fourth "And" gate; and means for connecting said output of said first shift register to said second input of said fourth "And" gate.