Memory access control circuit

Abstract

In a control unit having a read only memory, a control program is provided which has provision for all features with which the machine may be equipped and for a selected number of future features. The control program contains one or more mainline control loops which interrogate mainline and feature functions sequentially to determine whether a function requires service. If a function is present and requires service, the appropriate routine is executed whereafter the mainline control program proceeds to execute the next indicated control program instruction. If a function is present, but does not require service, a normal return or other procedure is executed to return to the control loop. When a feature is addressed which is not present, a feature return is executed forcing the control program back to the instruction following the last branch.

What is claimed is: 
     
       1. A microprogrammed processor for a data handling device including a read only control store and an execution register for receiving and storing the output of said control store in response to an address and comprising: address means including an instruction address register connected to said control store for supplying an address to said control store and including next address identifying means for identifying the next address to be gated to said instruction address register,   said next address identifying means including means for incrementing the current address and means for storing such incremented address upon command in an address recall register, said next address identifying means further including means for gating to said address register said incremented address stored during a prior processor instruction cycle,   said next address identifying means further including decode means operatively connected to the output of said execution register for selecting the next address to be gated to said instruction address register from the group including the said incremented current address, a new address, and said prior stored incremented address,   logic means connected to the output of predetermined bit positions of said execution register for determining the next address operation and outputting a binary signal indicative of such operation,   said logic means including circuit means connected to the output of said execution register to cause an output from said circuit means indicative of zero logic levels at all execution register bit positions to override the output of said logic means and produce a signal at the output of said logic means indicative of the operation which gates said prior stored incremented address to the instruction address register.   
     
     
       2. The microprogrammed processor of claim 1 wherein said circuit means comprises an AND circuit connected to the outputs of selected bit positions of said execution register less than the total number of said execution register bit positions,   such bit positions being selected as being indicative of the existence of a zero logic level at all execution register bit positions when a zero logic level is resident at all selected bit positions.