Video retimer system

Abstract

A time delay period between a first signal and a delayed second signal is iminated, restoring the original time relationship between the two signals as derived from a common trigger signal which may vary in its repetition rate. Known, uniform time increments are defined by a constant frequency source producing pulses connectable to both a static shift register having a predetermined number of bits, and a counter having its maximum cumulative count set at the sum of the predetermined number of bits in the shift register and the number of uniform time increments in the time delay period between the first and second signals. The common trigger signal is operative to simultaneously connect the source of clocking pulses to actuate both the shift register and the counter. Upon reception the delayed second signal is connected to the input of the shift register and upon reaching the maximum cumulative count of the counter, the clocking pulses are disconnected from both the shift register and the counter. At the next successive trigger signal, the shift register is reactuated to produce a retimed second signal restored to its original time disposition relative to the first signal.

What is claimed is: 
     
       1. A retiming system for eliminating a time delay period between a first signal and a delayed second signal to restore their synchronous relationship as derived from a repetitive common trigger signal comprising: a source of constant frequency clocking pulses defining known uniform time increments;   a static shift register having a predetermined number of bits;   a counter having means for selectively setting its maximum cumulative count at the sum of said predetermined number of bits and the number of said known uniform time increments in said time delay period;   means responsive to said common trigger signal for simultaneously connecting said source of constant frequency clocking pulses to actuate said shift register and said counter;   means connecting the subsequently occurring said delayed second signal to the input of said shift register;   means responsive to the selectively set maximum cumulative count of said counter for simultaneously disconnecting said source of constant frequency clocking pulses from said shift register and said counter leaving said delayed second signal in said shift register with a remaining number of unshifted bits representative of the time interval between said common trigger signal and said first signal; and   means receiving the output of said shift register after its reactuation in response to the next successive trigger signal, shifting said remaining number of unshifted bits for generating a retimed second signal in synchronism with the next successive first signal.   
     
     
       2. A retiming system as claimed in claim 1 including means connected to receive said first signal and said retimed second signal for displaying both said signals simultaneously. 
     
     
       3. A retiming system as claimed in claim 1 wherein the time period between successive common trigger signals is variable. 
     
     
       4. A retiming system as claimed in claim 1 wherein the setting of said maximum cumulative count of said counter represents a time period of less than the shortest time period between successive common trigger signals. 
     
     
       5. A retiming system as claimed in claim 1 wherein said source of constant frequency clocking pulses comprises a clock having its output divided by a frequency divider to produce said known uniform time increments. 
     
     
       6. A retiming system as claimed in claim 5 wherein said means responsive to said common trigger is an AND gate connected between said clock and said frequency divider. 
     
     
       7. A retiming system as claimed in claim 6 wherein said means responsive to the selectively set maximum cumulative count of said counter is a flip-flop for disabling said AND gate.