Data separator with compensation circuit

Abstract

A compensation circuit for providing output clock pulses which are accurately spaced timewise with respect to data times at which raw data pulses normally exist on a raw data line assuming no time shifting due to transmission difficulties and including a voltage controlled oscillator and a charge pump circuit for providing a changing voltage applied to the oscillator, and means for providing down and up change frequency signals applied to the charge pump circuit, the up change frequency signal being initiated at the leading edge of a raw data pulse on the raw data line when the raw data pulse is in normal position or is early or late and the down change frequency signal being initiated when the up change frequency signal terminates and terminating midway between data times.

I claim: 
     
       1. Circuitry for producing a data clock pulse for each data time at which a data pulse may normally exist on a raw data input line with the data pulses being shiftable timewise from their normal data times to be abnormal timewise, said circuitry comprising a variable frequency controlled oscillator for producing clock pulses, first means responsive to clock pulses from said variable frequency controlled oscillator for producing bit shift limit signals, second means responsive to clock pulses from said variable frequency controlled oscillator for producing data time signals, means responsive to said clock pulses, said limit signals and said data time signals for producing said data clock pulses, means for producing a first change frequency signal effective on said variable frequency oscillator to change the frequency in one direction and initiated under the control of a raw data pulse on said raw data line and terminated at said bit shift limit, means for initiating a second change frequency signal effective on said oscillator for changing the frequency of the oscillator in the opposite direction and initiated under control of termination of said first change frequency signal and terminated with the termination of a clock pulse from said variable frequency oscillator, and means for applying said first and second change frequency signals to said variable frequency oscillator whereby the frequency thereof is first increased and then decreased to provide a net change in frequency based upon the difference between time durations of said first and second change frequency signals. 
     
     
       2. The circuitry as set forth in claim 1 wherein said means for applying said first and second change frequency signals to said variable frequency oscillator includes a charge pump for changing the voltage applied to the oscillator under the control of said first and second change frequency signals. 
     
     
       3. The circuitry as set forth in claim 2, said charge pump including a first capacitor which is charged under the control of said first change frequency signals and another capacitor which is discharged under the control of said second change frequency signal, and a single source of electromotive force applicable to both of said capacitors for charging said first capacitor and for discharging said another capacitor. 
     
     
       4. Correction circuitry for generating increase and decrease frequency correction signals for a clock in data separator functioning to distinguish one bits occurring within a bit cell from clock bits occurring at the edge of a bit cell, the improvement comprising: means for providing repetitively occurring pulses defining data times,   means for generating limit signals defining bit shift and clock shift limits,   means responsive to pulses representing one bits and clock bits for generating increase frequency correction signals having durations dependent upon their occurrence relative to said data times and clock times and terminating and at said bit shift and clock shift limits,   means for generating fixed duration decrease frequency correction signals in response to termination of said increase frequency correction signals, and   means for applying said increase and decrease frequency correction signals to said clock circuit whereby the frequency thereof is first increased and then decreased to provide a net change in frequency based upon the difference between time durations of said increase and decrease frequency correction signals.   
     
     
       5. The correction circuitry of claim 4 wherein said increase frequency correction signals have a longer duration when said one bits occur prior to than when occurring after said data times. 
     
     
       6. The correction circuitry of claim 4 wherein said data times are defined by the fall of said repetitively occurring pulses. 
     
     
       7. The correction circuitry of claim 4 wherein said data times occur at the center of said bit cells.