Input-output system having cyclical scanning of interrupt requests

Abstract

A system is disclosed for controlling access to a central information processor by a plurality of peripheral devices. The system determines access on the basis of a (1) predetermined hierarchical priority order and (2) a cyclical scanning process. To achieve this, a system of hierarchically organized priority levels is combined with a system of cyclical scanning in a manner such that no single device may monopolize the central processor.

What is claimed is: 
     
       1. In an electronic computer having a plurality of input/output channels for connection of a corresponding plurality of peripheral control units to a central processor, a system for acknowledging input/output interrupt requests sent by said peripheral control units to the central processor comprising: a first ordered plurality of interrupt wires, each for transmitting first level interrupt request signals from a corresponding one of said peripheral control units to said central processor;   a second ordered plurality of interrupt wires, each for transmitting second level interrupt request signals from a corresponding one of said peripheral control units to said central processor;   a plurality of gates, one for each of said interrupt wires, for gating the signal flow over said wires;   scanning means coupled to said gates for enabling in sequence, one at a time, said gates;   first control means coupled to said scanning means and responsive to said gates for stopping said scanning means when an interrupt request signal is passed through one of said gates;   second control means for resetting said scanning means in a predetermined status following an interrupt request passed through one of said gates on said first plurality of interrupt wires and for activating said scanning means from said predetermined status in response to the falling off of said interrupt request passed through said one of said gates; and   third control means for activating said scanning means in response to the falling off of an interrupt request passed through one of said gates on said second plurality of interrupt wires.   
     
     
       2. The system of claim 1 wherein said scanning means comprises: switching means for generating a first and a second signal;   oscillating means responsive to said switching means for generating a series of clock signals, said oscillating means turning on in response to said first signals and said oscillating means turning off in response to said second signals;   counting means responsive to said clock signals; and   decoding means coupled to said counting means and including a plurality of ordered output lines, each output line coupled to one of said gates, an enabling signal appearing on each of said output lines in sequential order.   
     
     
       3. The system of claim 2 wherein said first control means further comprises: first gating means coupled to receive output signals from said gates and coupled to said switching means for causing said switching means to generate said second signal.   
     
     
       4. The system of claim 2 wherein said second control means comprises: second gating means coupled to receive output signals from said gates coupled to said first plurality of interrupt wires, said second gating means coupled to said switching means for causing said switching means to generate said first signal; and   reset means responsive to said second gating means and coupled to said counting means for generating a reset signal for said counting means.   
     
     
       5. The system of claim 2 wherein said third control means comprises: third gating means coupled to receive output signals from said gates coupled to said second plurality of interrupt wires, said third gating means coupled to said switching means for causing said switching means to generate said first signal.   
     
     
       6. In an electronic computer having a plurality of peripheral control units for connection to a central processor, a system for acknowledging input/output interrupt request signals sent by said peripheral control units to said central processor comprising: a plurality of input/output channels, each of said channels coupling one of said peripheral control units to said central processor, said channels including: a first plurality of interrupt wires, each for transmitting first level interrupt request signals from one of said pripheral control units to said central processor;   a second plurality of interrupt wires, each for transmitting second level interrupt request signals from one of said peripheral control units to said central processor;   a third plurality of interrupt wires, each for transmitting third level interrupt request signals from one of said peripheral control units to said central processor;     a priority selecting network coupled to said first plurality of interrupt wires for acknowledging the first level interrupt request signal having the highest priority among all the first level interrupt request signals appearing on said first plurality of wires;   a plurality of gates, one for each of said wires of said second and said third pluralities of interrupt wires for controlling the signal flow over said wires;   scanning means coupled to said gates for enabling in sequence, one at a time, said gates;   first control means coupled to said scanning means and responsive to said gates for stopping said scanning means when an interrupt request signal has passed through one of said wires;   second control means for resetting said scanning means in a predetermined status following one of said second level interrupt request signals being passed through one of said gates coupled to said second plurality of interrupt wires and for activating said scanning means from said predetermined status in response to the falling off of said one second level interrupt request signal; and   third control means connected to said gates coupled to said wires of said third plurality for activating said scanning means in response to the falling off of one of said third level interrupt request signals.   
     
     
       7. The system of claim 6 wherein said scanning means comprises: switching means for generating a first and a second signal;   oscillating means responsive to said switching means for generating a series of clock signals, said oscillating means turning on in response to said first signals and said oscillating means turning off in response to said second signals;   counting means responsive to said clock signals; and   decoding means coupled to said counting means and including a plurality of ordered output lines, each output line coupled to one of said gates, an enabling signal appearing on each of said output lines in sequential order.   
     
     
       8. The system of claim 7 wherein said first control means comprises: first gating means coupled to receive output signals from said gates and coupled to said switching means for causing said switching means to generate said second signal.   
     
     
       9. The system of claim 7 wherein said second control means comprises: second gating means coupled to receive output signals from said gates coupled to said second plurality of interrupt wires, said second gating means coupled to said switching means for causing said switching means to generate said first signal; and   reset means responsive to said second gating means and coupled to said counting means for generating a reset signal for said counting means.   
     
     
       10. The system of claim 7 wherein said third control means comprises: third gating means coupled to receive output signals from said gates coupled to said third plurality of interrupt wires, said third gating means coupled to said switching means for causing said switching means to generate said first signals.