High voltage switch circuitry and non-volatile memory device including the same

Abstract

A high voltage switch circuitry of a non-volatile memory device includes a first pass transistor, a depletion mode transistor, a level shifter and a first voltage source. The first pass transistor configured to transfer a driving voltage to an output terminal connected to a second pass transistor of the non-volatile memory device, upon being turned on based on its gate receiving a negative voltage. The depletion mode transistor configured to provide the first pass transistor with the driving voltage based on an output signal fed back from the output terminal. The level shifter applies a voltage to the gate of the first pass transistor. The first voltage source supplies the negative voltage less than the ground voltage to the level shifter. The level shifter is further configured to apply the negative voltage from the first voltage source to the gate of the first pass transistor.

What is claimed is: 
     
         1 . A high voltage switch circuitry of a non-volatile memory device, comprising:
 a first pass transistor configured to transfer a driving voltage to an output terminal connected to a second pass transistor of the non-volatile memory device, upon being turned on based on its gate receiving a negative voltage;   a depletion mode transistor configured to provide the first pass transistor with the driving voltage based on an output signal fed back from the output terminal;   a level shifter configured to apply a voltage to the gate of the first pass transistor; and   a first voltage source configured to supply the negative voltage smaller than a ground voltage to the level shifter,   wherein the level shifter is further configured to apply the negative voltage from the first voltage source to the gate of the first pass transistor.   
     
     
         2 . The high voltage switch circuitry according to  claim 1 , wherein,
 in response to the ground voltage being applied to a gate of the depletion mode transistor, the depletion mode transistor is configured to transfer a first source voltage corresponding to a difference between a threshold voltage of the depletion mode transistor and the ground voltage to a source of the first pass transistor, and   in response to the first pass transistor receiving the first source voltage and the negative voltage, the first pass transistor is turned on and transfers a first positive voltage to the gate of the depletion mode transistor.   
     
     
         3 . The high voltage switch circuitry according to  claim 2 , wherein,
 in response to receiving the first positive voltage, the depletion mode transistor is configured to transfer a second source voltage to the source of the first pass transistor,   in response to receiving the second source voltage, the first pass transistor is configured to transfer a second positive voltage to the gate of the depletion mode transistor,   the second source voltage is greater than the first source voltage, and   the second positive voltage is greater than the first positive voltage.   
     
     
         4 . The high voltage switch circuitry according to  claim 2 , wherein a difference between the first source voltage and the negative voltage is greater than a threshold voltage of the first pass transistor. 
     
     
         5 . The high voltage switch circuitry according to  claim 2 ,
 wherein the first voltage source is configured to supply the negative voltage to the level shifter for a predetermined time, and   wherein the first pass transistor is turned on at any point during the predetermined time.   
     
     
         6 . The high voltage switch circuitry according to  claim 5 , wherein the first voltage source is further configured to supply the ground voltage to the level shifter after the predetermined time. 
     
     
         7 . The high voltage switch circuitry according to  claim 2 ,
 wherein a first threshold voltage of the first pass transistor is greater than an initial threshold voltage of the first pass transistor, and   wherein the first source voltage is greater than the initial threshold voltage and less than the first threshold voltage.   
     
     
         8 . The high voltage switch circuitry according to  claim 7 , wherein, if a threshold voltage of the first pass transistor is greater than the difference between the first source voltage and the ground voltage, the first voltage source is configured to supply the negative voltage to the level shifter. 
     
     
         9 . The high voltage switch circuitry according to  claim 2 , wherein the difference between the first source voltage and the ground voltage is less than a threshold voltage of the first pass transistor. 
     
     
         10 . The high voltage switch circuitry according to  claim 1 , further comprising a second voltage source configured to supply a power supply voltage to the level shifter, wherein
 the level shifter is configured to provide the gate of the first pass transistor with the voltage received from the first voltage source or the voltage received from the second voltage source, based on an enable signal and an inverted enable signal.   
     
     
         11 . The high voltage switch circuitry according to  claim 10 , wherein, in response to the enable signal at a high level and the inverted enable signal at a low level, the level shifter is configured to provide the gate of the first pass transistor with the voltage received from the first voltage source. 
     
     
         12 . The high voltage switch circuitry according to  claim 10 , wherein, in response to the enable signal at a low level and the inverted enable signal at a high level, the level shifter is configured to provide the gate of the first pass transistor with the voltage received from the second voltage source. 
     
     
         13 . The high voltage switch circuitry according to  claim 12 , wherein, in response to the level shifter providing the gate of the first pass transistor with the voltage received from the second voltage source, the first pass transistor is turned off. 
     
     
         14 . The high voltage switch circuitry according to  claim 10 , further comprising
 a logic circuit configured to generate the enable signal based on an input signal and a control signal and transfer the generated enable signal to the level shifter.   
     
     
         15 . The high voltage switch circuitry according to  claim 14 , further comprising an inverter configured to receive the enable signal from the logic circuit, generate the inverted enable signal, and transfer the generated inverted enable signal to the level shifter. 
     
     
         16 . A high voltage switch circuitry of a non-volatile memory device, comprising:
 a pass transistor configured to transfer a driving voltage to an output terminal upon being turned;   a depletion mode transistor configured to provide a first source voltage to a source of the pass transistor in response to receiving a ground voltage at its gate;   a level shifter configured to apply a voltage to the gate of the first pass transistor; and   a first voltage source configured to supply a negative voltage smaller than the ground voltage to the level shifter,   wherein in response to the pass transistor receiving the first source voltage and the negative voltage to its gate, the pass transistor is configured to turn on and transfer a first positive voltage to the gate of the depletion mode transistor,   wherein a difference between the first source voltage and the negative voltage is greater than a threshold voltage of the pass transistor,   wherein the first voltage source is configured to supply the negative voltage to the level shifter for a predetermined time,   wherein the first transistor is configured to turn on at any point during the predetermined time, and   wherein after the predetermined time, the first voltage source is further configured to supply the ground voltage to the level shifter.   
     
     
         17 . A non-volatile memory device, comprising:
 a memory cell array comprising memory cells connected to a word line;   a voltage generator configured to generate a first high voltage;   a first pass transistor connected to the word line; and   a high voltage switch circuitry configured to boost the first high voltage to a second high voltage and provide the second high voltage to a gate of the first pass transistor, wherein   the high voltage switch circuitry comprises:
 a second pass transistor configured to transfer a driving voltage to an output terminal connected to the first pass transistor, upon being turned on based on its gate receiving a negative voltage; 
 a depletion mode transistor configured to provide the second pass transistor with the driving voltage based on an output signal fed back from the output terminal; 
 a level shifter configured to apply a voltage to the gate of the second pass transistor; and 
 a first voltage source configured to supply the negative voltage smaller than a ground voltage to the level shifter, 
   wherein the level shifter is further configured to apply the negative voltage supplied from the first voltage source to the gate of the second pass transistor.   
     
     
         18 . The non-volatile memory device according to  claim 17 , wherein
 a difference between the first source voltage and the negative voltage is greater than a threshold voltage of the second pass transistor, and   a difference between the first source voltage and the ground voltage is less than the threshold voltage.   
     
     
         19 . The non-volatile memory device according to  claim 17 , wherein, in response to the high voltage switch circuitry providing the gate of the first pass transistor with the second high voltage, the first pass transistor is configured to transfer the first high voltage to the word line. 
     
     
         20 . The non-volatile memory device according to  claim 17 , wherein the first high voltage is a program voltage, a pass voltage, or an erase voltage for a selected memory block in the memory cell array.