Semiconductor device and method of communication by semiconductor device

Abstract

In one or more aspects, a semiconductor device includes a processing circuitry and N signal paths corresponding to N communication lanes. The processing circuitry is configured to obtain lane defect information indicating L defective lanes or (N−L) functional lanes among the N communication lanes; apply a remapping configuration corresponding to a mapping relationship between a flow control unit (flit) protocol format having M rows of N data units and a flit reassemble format having (M+R) rows of (N−L) data units; and obtain a target flit in the flit protocol format and transmit data units of the target flit through (N−L) functional lanes based on the flit reassemble format, or receive the data units of the target flit through the (N−L) functional lanes based on the flit reassemble format and obtain the target flit in the flit protocol format.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a processing circuitry; and   N signal paths corresponding to N communication lanes, N being a positive integer,   wherein the processing circuitry is coupled to the N signal paths, and the processing circuitry is configured to:
 obtain lane defect information indicating L defective lanes among the N communication lanes, or indicating (N−L) functional lanes among the N communication lanes, L being zero or a positive integer; 
 based on L being greater than zero and based on the lane defect information, apply a remapping configuration corresponding to a mapping relationship between a flow control unit (flit) protocol format having M rows of N data units and a flit reassemble format having (M+R) rows of (N−L) data units, M being a positive integer, and R being a positive integer; 
 based on L being greater than zero and based on the remapping configuration:
 obtain a target flit in the flit protocol format and transmit data units of the target flit through (N−L) functional lanes based on the flit reassemble format; or 
 receive the data units of the target flit through the (N−L) functional lanes based on the flit reassemble format and obtain the target flit in the flit protocol format. 
 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the processing circuitry is configured to:
 sequentially map N data units per row, M rows in total, in the flit protocol format to (N−L) data units per row, (M+R) rows in total, in the flit reassemble format.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the processing circuitry is configured to:
 map (N−L) data units per row, M rows in total, in the flit protocol format that correspond to the (N−L) functional lanes to (N−L) data units per row, M rows in total, in the flit reassemble format based on original row and lane assignments in the flit protocol format; and   map M×L data units in the flit protocol format that correspond to the L defective lanes to up to R extra rows in the flit reassemble format.   
     
     
         4 . The semiconductor device of  claim 1 , wherein the processing circuitry is further configured to:
 receive one or more test flits through the N communication lanes from another processing circuitry;   identify the L defective lanes or the (N−L) functional lanes among the N communication lanes based on reception of the one or more test flits; and   transmit, through a control interface, the lane defect information to the other processing circuitry, the lane defect information indicating the L defective lanes or the (N−L) functional lanes.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the processing circuitry is further configured to:
 transmit one or more test flits through the N communication lanes to another processing circuitry; and   receive, through a control interface, the lane defect information from the other processing circuitry, the lane defect information indicating the L defective lanes or the (N−L) functional lanes.   
     
     
         6 . The semiconductor device of  claim 1 , wherein
 each one of the data units corresponds to a byte,   N ranges from 32 to 128,   M ranges from 1 to 8, and   R ranges from 1 to 4.   
     
     
         7 . The semiconductor device of  claim 1 , wherein
 each one of the data units corresponds to a byte,   the target flit includes 256 bytes,   N is 64,   M is 4, and   R is 1.   
     
     
         8 . A method of communication by a processing circuitry of a semiconductor device, comprising:
 obtaining lane defect information indicating L defective lanes among N communication lanes accessible by the processing circuitry, or indicating (N−L) functional lanes among the N communication lanes, N being a positive integer, and L being zero or a positive integer,   based on L being greater than zero and based on the lane defect information, applying a remapping configuration corresponding to a mapping relationship between a flow control unit (flit) protocol format having M rows of N data units and a flit reassemble format having (M+R) rows of (N−L) data units, M being a positive integer, and R being a positive integer; and   based on L being greater than zero and based on the remapping configuration:
 obtaining a target flit in the flit protocol format and transmitting data units of the target flit through (N−L) functional lanes based on the flit reassemble format; or 
 receiving the data units of the target flit through the (N−L) functional lanes based on the flit reassemble format and obtaining the target flit in the flit protocol format. 
   
     
     
         9 . The method of  claim 8 , wherein the mapping relationship corresponds to:
 sequentially mapping N data units per row, M rows in total, in the flit protocol format to (N−L) data units per row, (M+R) rows in total, in the flit reassemble format.   
     
     
         10 . The method of  claim 8 , wherein the mapping relationship corresponds to:
 mapping (N−L) data units per row, M rows in total, in the flit protocol format that correspond to the (N−L) functional lanes to (N−L) data units per row, M rows in total, in the flit reassemble format based on original row and lane assignments in the flit protocol format; and   mapping M×L data units in the flit protocol format that correspond to the L defective lanes to up to R extra rows in the flit reassemble format.   
     
     
         11 . The method of  claim 8 , further comprising:
 receiving one or more test flits through the N communication lanes from another processing circuitry;   identifying the L defective lanes or the (N−L) functional lanes among the N communication lanes based on reception of the one or more test flits; and   transmitting, through a control interface, the lane defect information to the other processing circuitry, the lane defect information indicating the L defective lanes or the (N−L) functional lanes.   
     
     
         12 . The method of  claim 8 , further comprising:
 transmitting one or more test flits through the N communication lanes to another processing circuitry; and   receiving, through a control interface, the lane defect information from the other processing circuitry, the lane defect information indicating the L defective lanes or the (N−L) functional lanes.   
     
     
         13 . The method of  claim 8 , wherein
 each one of the data units corresponds to a byte,   N ranges from 32 to 128,   M ranges from 1 to 8, and   R ranges from 1 to 4.   
     
     
         14 . The method of  claim 8 , wherein
 each one of the data units corresponds to a byte,   the target flit includes 256 bytes,   N is 64,   M is 4, and   R is 1.   
     
     
         15 . A semiconductor device, comprising:
 a dynamic remapping circuitry;   a protocol circuitry; and   a front end circuitry configured to transmit or receive data units of a target flow control unit (flit) through N communication lanes, N being a positive integer,   wherein the dynamic remapping circuitry is coupled to the protocol circuitry and the front end circuitry, and the dynamic remapping circuitry is configured to:
 obtain lane defect information indicating L defective lanes among the N communication lanes, or indicating (N−L) functional lanes among the N communication lanes, L being zero or a positive integer; 
 based on L being greater than zero and based on the lane defect information, apply a remapping configuration corresponding to a mapping relationship between a flit protocol format having M rows of N data units and a flit reassemble format having (M+R) rows of (N−L) data units, M being a positive integer, and R being a positive integer; 
 based on L being greater than zero and based on the remapping configuration:
 receive the target flit in the flit protocol format from the protocol circuitry and transmit the data units of the target flit through the (N−L) functional lanes based on the flit reassemble format; or 
 receive the data units of the target flit through the (N−L) functional lanes based on the flit reassemble format and transmit the target flit in the flit protocol format to the protocol circuitry. 
 
   
     
     
         16 . The semiconductor device of  claim 15 , wherein the dynamic remapping circuitry is configured to:
 sequentially map N data units per row, M rows in total, in the flit protocol format to (N−L) data units per row, (M+R) rows in total, in the flit reassemble format.   
     
     
         17 . The semiconductor device of  claim 15 , wherein the dynamic remapping circuitry is configured to:
 map (N−L) data units per row, M rows in total, in the flit protocol format that correspond to the (N−L) functional lanes to (N−L) data units per row, M rows in total, in the flit reassemble format based on original row and lane assignments in the flit protocol format; and   map M×L data units in the flit protocol format that correspond to the L defective lanes to up to R extra rows in the flit reassemble format.   
     
     
         18 . The semiconductor device of  claim 15 , further comprising:
 a control interface; and   a lane defect detection circuitry configured to:
 receive one or more test flits through the N communication lanes from another processing circuitry; 
 identify the L defective lanes or the (N−L) functional lanes among the N communication lanes based on reception of the one or more test flits; and 
 transmit, through the control interface, the lane defect information to the other processing circuitry, the lane defect information indicating the L defective lanes or the (N−L) functional lanes. 
   
     
     
         19 . The semiconductor device of  claim 15 , further comprising:
 a control interface; and   a lane defect detection circuitry configured to:
 transmit one or more test flits through the N communication lanes to another processing circuitry; and 
 receive, through the control interface, the lane defect information from the other processing circuitry, the lane defect information indicating the L defective lanes or the (N−L) functional lanes. 
   
     
     
         20 . The semiconductor device of  claim 15 , wherein
 each one of the data units corresponds to a byte,   N ranges from 32 to 128,   M ranges from 1 to 8, and   R ranges from 1 to 4.