Control Method and Apparatus for Memory, and Electronic Device

Abstract

The apparatus includes transistors and a memory cell array. Memory cells located in a same column are coupled to a same transistor and a same word line, the transistors are coupled to a bit line, and memory cells located in a same row are coupled to a same plate line. The method includes turning on a transistor coupled to an unselected word line, applying a first voltage V1 to a bit line and applying a second voltage V2 to an unselected plate line, and using a selected word line, turning on a transistor coupled to the selected word line, applying a third voltage V3 to the bit line, and applying a fourth voltage V4 to a selected plate line, |V4−V3|=Vw, |V4−V1|<½Vw, |V3−V2|<½Vw.

1 . A memory control method comprising:
 in a first sub-phase of an active phase of a target memory cell, conducting, through an unselected word line, a first transistor coupled to the unselected word line, applying a first voltage V1 to a bit line, and applying a second voltage V2 to an unselected plate line; and   in a second sub-phase of the active phase, conducting, through a selected word line, a second transistor coupled to the selected word line, applying a third voltage V3 to the bit line, and applying a fourth voltage V4 to a selected plate line, and controlling the voltages such that a word line voltage Vw=|V4−V3|, |V4−V1|<½Vw, and |V3−V2|<½Vw.   
     
     
         2 . The memory control method of  claim 1 , further comprising controlling the voltages such that |V4−V1|=|V3−V2|=|V1−V2|=(⅓)Vw. 
     
     
         3 . The memory control method of  claim 1 , further comprising:
 writing, using the active phase, first data into the target memory cell, wherein V4=Vw, V3=0, V2=(⅓)Vw, and V1=(⅔)Vw; or   writing, using the active phase, second data into the target memory cell, wherein V4=0, V3=Vw, V2=(⅔)Vw, and V1=(⅓)Vw.   
     
     
         4 . The memory control method of  claim 3 , wherein, before applying the fourth voltage V4, the memory control method further comprises:
 cutting off, through the selected word line, the second transistor;   after applying the fourth voltage V4, activating, through the selected word line, the second transistor in a third sub-phase of the active phase; and   storing first target data of the target memory cell into a sense amplifier based on a voltage of the bit line, wherein the first target data is the second data or the first data.   
     
     
         5 . The memory control method of  claim 4 , further comprising reading the first target data from the sense amplifier in a read phase of the target memory cell. 
     
     
         6 . The memory control method of  claim 4 , further comprising:
 deleting the first target data from the sense amplifier; and   writing second target data to the sense amplifier in a write phase of the target memory cell, wherein the second target data is the second data or the first data.   
     
     
         7 . The memory control method of  claim 5 , wherein data in the sense amplifier is the second data, and wherein the memory control method further comprises:
 activating, in a first sub-phase of a precharge phase, through the unselected word line, the first transistor;   applying the second voltage V2 to the bit line;   applying the first voltage V1 to the unselected plate line;   activating, in a second sub-phase of the precharge phase, through the selected word line, the second transistor;   applying the fourth voltage V4 to the bit line; and   applying the third voltage V3 to the selected plate line.   
     
     
         8 . The memory control method of  claim 5 , wherein data in the sense amplifier is the first data, and wherein the memory control method further comprises:
 activating, in a first sub-phase of a precharge phase, through the unselected word line, the first transistor;   applying the second voltage V2 to the bit line;   applying the first voltage V1 to the unselected plate line;   activating, in a second sub-phase of the precharge phase, through the selected word line, the second transistor;   applying the second voltage V2 to the bit line; and   applying the third voltage V3 to the selected plate line.   
     
     
         9 . The memory control method of  claim 1 , further comprising separately applying the first voltage V1 to the bit line, the selected plate line, and the unselected plate line in a third sub-phase of a precharge phase to initialize the bit line, the selected plate line, and the unselected plate line. 
     
     
         10 . The memory control method of  claim 1 , further comprising obtaining the first voltage and the second voltage by performing voltage division on an initial voltage according to different ratios. 
     
     
         11 . An electronic apparatus comprising:
 a memory comprising:
 a bit line; 
 a plurality of transistors coupled to the bit line; 
 a plurality of word lines; 
 a memory cell array comprising memory cells, wherein the memory cells located in a same column in the memory cell array are coupled to a same transistor or the transistors and a same word line of the word lines; and 
 a plurality of plate lines, wherein the memory cells located in a same row in the memory cell array are coupled to a selected plate line of the plate lines; and 
   control apparatus coupled to the memory and comprising:
 a first control circuit configured to activate, in a first sub-phase of an active phase of a target memory cell and through an unselected word line, a first transistor of the transistors and coupled to the unselected word line, apply a first voltage V1 to the bit line, and apply a second voltage V2 to an unselected plate line; and 
 a second control circuit, configured to activate, in a second sub-phase of the active phase, through a selected word line, a second transistor of the transistors and coupled to the selected word line, apply a third voltage V3 to the bit line, and apply a fourth voltage V4 to the selected plate line, wherein word line voltage Vw=|V4−V3|, |V4−V1|<½Vw, and |V3−V2|<½Vw. 
   
     
     
         12 . The electronic apparatus of  claim 11 , wherein |V4−V1|=|V3−V2|=|V1−V2|=(⅓)Vw. 
     
     
         13 . The electronic apparatus of  claim 11 , wherein the control apparatus is further configured to write first data into the target memory cell, V4=Vw, V3=0, V2=(⅓)Vw, and V1=(⅔) Vw; or write second data into the target memory cell, V4=0, V3=Vw, V2=(⅔)Vw, and V1=(⅓)Vw. 
     
     
         14 . The electronic apparatus of  claim 13 , wherein the memory further comprises a sense amplifier coupled to the bit line, wherein the control apparatus is further configured to write the first data into the target memory cell, and wherein the second control circuit is further configured to:
 before the fourth voltage V4 is applied to the selected plate line in the second sub-phase of the active phase, cut off, through the selected word line, the second transistor;   activate, through the selected word line, the second transistor in a third sub-phase of the active phase; and   store first target data of the target memory cell into the sense amplifier based on a voltage of the bit line, wherein the first target data is the second data or the first data.   
     
     
         15 . The electronic apparatus of  claim 14 , wherein the control apparatus further comprises a third control circuit configured to read the first target data from the sense amplifier in a read phase of the target memory cell. 
     
     
         16 . The electronic apparatus of  claim 14 , wherein the control apparatus further comprises a fourth control circuit configured to delete the first target data and write second target data into the sense amplifier in a write phase of the target memory cell, and wherein the second target data is the second data or the first data. 
     
     
         17 . The electronic apparatus of  claim 15 , wherein data in the sense amplifier is the second data, wherein the first control circuit is further configured to:
 in a first sub-phase of a precharge phase, activate the first transistor;   apply the second voltage V2 to the bit line; and   apply the first voltage V1 to the unselected plate line, and wherein   
       the second control circuit is further configured to:
 in a second sub-phase of the precharge phase, activate the second transistor; 
 apply the fourth voltage V4 to the bit line; and 
 apply the third voltage V3 to the selected plate line. 
 
     
     
         18 . The electronic apparatus of  claim 15 , wherein data in the sense amplifier is the first data, wherein the first control circuit is further configured to:
 in a first sub-phase of a precharge phase, activate the first transistor line;   apply the second voltage V2 to the bit line; and   apply the first voltage V1 to the unselected plate line, and wherein   
       the second control circuit is further configured to:
 in a second sub-phase of the precharge phase, activate the second transistor; 
 apply the second voltage V2 to the bit line; and 
 apply the third voltage V3 to the selected plate line. 
 
     
     
         19 . The electronic apparatus of  claim 11 , wherein the control apparatus further comprises a fifth control circuit configured to separately apply the first voltage V1 to the bit line, the selected plate line, and the unselected plate line in a third sub-phase of a precharge phase to initialize the bit line, the selected plate line, and the unselected plate line. 
     
     
         20 . The electronic apparatus of  claim 11 , wherein the first control circuit further comprises a voltage divider circuit configured to perform voltage division on an initial voltage according to different ratios, to obtain the first voltage and the second voltage.