Interrupt register stacking within a data processing system

Abstract

A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.

1 . A processor, comprising:
 fetch circuitry configured to fetch instructions, wherein the fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt; and   a speculation control circuit configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, wherein a register tracking value is updated with each speculative push.   
     
     
         2 . The processor of  claim 1 , wherein the predetermined register order comprises a predetermined register order of general purpose registers (GPRs) of the processor. 
     
     
         3 . The processor of  claim 1 , wherein the register tracking value represents a count value of a number of registers pushed onto the memory stack. 
     
     
         4 . The processor of  claim 3 , wherein the register tracking value is provided by a counter within the speculation control circuit. 
     
     
         5 . The processor of  claim 3 , wherein the register tracking value is provided by a pointer value which points to a list of registers in the predetermined register order. 
     
     
         6 . The processor of  claim 1 , wherein the speculative pushing is begun prior to execution of the first interrupt handler instruction. 
     
     
         7 . The processor of  claim 1 , further comprising execution circuitry, wherein the first handler instruction is a register push instruction and the execution circuitry is configured to, when executing the register push instruction, non-speculatively push registers for the register push instruction onto the memory stack in accordance with the predetermined register order, wherein the speculation control circuit continues to update the register tracking value with each non-speculative push for the register push instruction. 
     
     
         8 . The processor of  claim 7 , wherein the non-speculative pushing of the registers in response to the register push instruction continues with a register of the predetermined register order indicated by the register tracking value, such that a first portion of registers in the predetermined register order is speculatively pushed prior to completion of the fetch of the first interrupt handler instruction and a second portion of registers in the predetermined register order is non-speculatively pushed in response to executing the first interrupt handler instruction, wherein the first and second portions of registers do not overlap. 
     
     
         9 . The processor of  claim 8 , wherein the non-speculatively pushing the registers in response to executing the register push instruction is continued until a total number of registers has been pushed, wherein the total number is indicated by the register push instruction. 
     
     
         10 . The processor of  claim 7 , wherein the speculative pushing of registers prior to the completion of the fetch of the first interrupt handler instruction continues until a predetermined maximum number of speculative pushes has been reached. 
     
     
         11 . The processor of  claim 7 , wherein the fetch circuitry is configured to, in response to a second interrupt received by the processor with a greater priority than the first interrupt, fetch a first interrupt handler instruction for the received second interrupt, wherein the speculative control circuit is configured to use the register tracking value to continue speculative pushing of registers onto the memory stack in accordance with the predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the second interrupt, wherein the register tracking value continues to be updated with each speculative push. 
     
     
         12 . The processor of  claim 7 , wherein the fetch circuitry is configured to fetch a second interrupt handler instruction for the first interrupt, wherein the second interrupt handler instruction for the first interrupt is a register pop instruction, and the execution circuitry is configured to:
 when executing the register pop instruction, pop registers from the memory stack in accordance with the predetermined register order in reverse, wherein the speculation control circuit updates the register tracking value with each pop.   
     
     
         13 . The processor of  claim 12 , wherein the execution circuitry is further configured to:
 when executing the register push instruction, after non-speculatively pushing registers for the register push instruction onto the memory stack in accordance with the predetermined register order, selectively push control and status registers onto the memory stack based on a preempt field of the register push instruction; and   when executing the register pop instruction, prior to popping registers from the memory stack in accordance with the predetermined register order in reverse, selectively pop the control and status registers based on a preempt field of the register pop instruction.   
     
     
         14 . The processor of  claim 12 , wherein the speculation control circuit is configured to, in response to a second interrupt received by the processor during execution of the register pop instruction:
 initiate a fetch of a first interrupt handler instruction for the second interrupt; and   speculatively push additional registers onto the memory stack in accordance with the predetermined register order starting from a previously pushed register as indicated by the register tracking value, and updating the register tracking value with each additional register push, wherein the speculative pushing of the additional registers is performed prior to completing the fetching of the first interrupt handler instruction for the second interrupt.   
     
     
         15 . In a processor, a method comprising:
 receiving a first interrupt during execution of a main program;   in response to the receiving the first interrupt:
 initiating a fetch of a first interrupt handler instruction for the first interrupt, and 
 initiating speculative pushing of general purpose registers (GPRs) onto a memory stack in accordance with a predetermined register order, wherein at least one GPR is speculatively pushed prior to completion of the fetch of the first interrupt handler instruction for the first interrupt; 
   incrementing a register tracking value with each GPR that is speculatively pushed;   completing the fetch of the first interrupt handler instruction, wherein the first interrupt handler instruction comprises a register push instruction which indicates a number of GPRs to be pushed for handling the first interrupt; and   non-speculatively pushing GPRs in response to the register push instruction onto the memory stack in accordance with the predetermined register order while a total number of speculatively and non-speculatively pushed GPRs is less than the number of GPRs indicated by the register push instruction, wherein the register tracking value is further incremented with each GPR that is non-speculatively pushed.   
     
     
         16 . The method of  claim 15 , wherein the speculative pushing of registers prior to the completion of the fetch of the first interrupt handler instruction continues until a predetermined maximum number of speculative pushes has been reached. 
     
     
         17 . The method of  claim 15 , further comprising:
 receiving a second interrupt while speculatively pushing or non-speculatively pushing of GPRs onto the stack, wherein the second interrupt has a higher priority than the first interrupt; and   in response to receiving the second interrupt:
 initiating a fetch of a first interrupt handler instruction for the second interrupt, and 
 using the register tracking value to continue speculative pushing of GPRs onto the memory stack in accordance with the predetermined register order, prior to completion of the fetch of the first interrupt handler instruction for the second interrupt, wherein the register tracking value continues to be incremented with each GPR that is speculatively pushed in response to receiving the second interrupt. 
   
     
     
         18 . The method of  claim 15 , further comprising:
 executing a second interrupt handler instruction for the first interrupt, wherein the second interrupt handler instruction comprises a register pop instruction;   popping GPRs from the memory stack in accordance with the predetermined register order in reverse; and   decrementing the register tracking value with each GPR that is popped in response to the register pop instruction.   
     
     
         19 . The method of  claim 18 , further comprising:
 receiving a second interrupt while popping registers in response to the register pop instruction;   in response to receiving the second interrupt:
 initiating a fetch of a first interrupt hander instruction for the second interrupt, and 
 speculatively pushing additional GPRs onto the memory stack in accordance with the predetermined register order starting from a previously pushed register as indicated by the register tracking value; and 
   incrementing the register tracking value with each additional register push.   
     
     
         20 . The method of  claim 15 , wherein the register tracking value represents a count value of a number of registers pushed onto the memory stack.