US2026082611A1PendingUtilityA1

Nitride semiconductor device

Assignee: PANASONIC HOLDINGS CORPPriority: May 23, 2023Filed: Nov 17, 2025Published: Mar 19, 2026
Est. expiryMay 23, 2043(~16.8 yrs left)· nominal 20-yr term from priority
H10D 30/478H10D 30/477H10D 64/252H10D 62/221H10D 62/117H10D 64/256H10D 30/475H10D 62/343H10D 62/8503H10D 30/87H10D 30/83H10D 30/60H10D 30/47H10D 30/051H10D 62/83H10D 30/061H10D 62/81
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Claims

Abstract

A nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a first p-type nitride semiconductor layer and a second nitride semiconductor layer disposed sequentially from below; an electron transport layer and an electron supply layer arranged sequentially from below to cover a first opening and the second nitride semiconductor layer, the first opening penetrating through the second nitride semiconductor layer and the first p-type nitride semiconductor layer; a second p-type nitride semiconductor layer or an insulating layer disposed in a position overlapping with a bottom surface of the first opening; a gate electrode disposed in a position overlapping with the second nitride semiconductor layer; a first source electrode disposed to cover a second opening penetrating through the electron supply layer and the electron transport layer; a drain electrode; and a second source electrode disposed above the second p-type nitride semiconductor layer or the insulating layer.

Claims

exact text as granted — not AI-modified
1 . A nitride semiconductor device comprising:
 a substrate;   a first nitride semiconductor layer disposed above the substrate;   a first p-type nitride semiconductor layer disposed above the first nitride semiconductor layer;   a second nitride semiconductor layer disposed above the first p-type nitride semiconductor layer;   an electron transport layer and an electron supply layer arranged sequentially from below to cover a lateral surface and a bottom surface of a first opening and an upper surface of the second nitride semiconductor layer, the first opening penetrating through the second nitride semiconductor layer and the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer;   a second p-type nitride semiconductor layer or an insulating layer disposed above the electron supply layer in a position overlapping with the bottom surface of the first opening in the planar view of the substrate;   a gate electrode disposed above the electron supply layer in a position overlapping with the second nitride semiconductor layer in the planar view of the substrate;   a first source electrode disposed to cover a second opening and electrically connected to the first p-type nitride semiconductor layer, the second opening being disposed in a position away from the gate electrode in the planar view of the substrate and penetrating through the electron supply layer and the electron transport layer and reaching the first p-type nitride semiconductor layer;   a drain electrode disposed below the substrate; and   a second source electrode disposed above the second p-type nitride semiconductor layer or the insulating layer and electrically connected to the first source electrode.   
     
     
         2 . The nitride semiconductor device according to  claim 1 ,
 wherein the lateral surface of the first opening is inclined relative to the bottom surface of the first opening,   an upper surface of the electron supply layer includes a flat portion along the bottom surface of the first opening and an inclined portion along the lateral surface of the first opening, and   the second p-type nitride semiconductor layer or the insulating layer continuously covers the flat portion and part of the inclined portion.   
     
     
         3 . The nitride semiconductor device according to  claim 1  further comprising:
 a third p-type nitride semiconductor layer disposed between the gate electrode and the electron supply layer to be spaced from the second p-type nitride semiconductor layer or the insulating layer. 
 
     
     
         4 . The nitride semiconductor device according to  claim 3 ,
 wherein in the planar view of the substrate, a distance between the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer is shorter than a distance between the third p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer.   
     
     
         5 . The nitride semiconductor device according to  claim 3 ,
 wherein in the planar view of the substrate, a distance between the third p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer is shorter than a distance between the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer.   
     
     
         6 . The nitride semiconductor device according to  claim 1 ,
 wherein a distance between the second p-type nitride semiconductor layer or the insulating layer and the drain electrode is shorter than a distance between the first p-type nitride semiconductor layer and the drain electrode.   
     
     
         7 . The nitride semiconductor device according to  claim 1 ,
 wherein the nitride semiconductor device comprises the second p-type nitride semiconductor layer among the second p-type nitride semiconductor layer and the insulating layer,   the second p-type nitride semiconductor layer is further disposed in a position overlapping with the lateral surface of the first opening in the planar view of the substrate,   the second source electrode is further electrically connected to the second p-type nitride semiconductor layer, and   part of a lower surface of the second p-type nitride semiconductor layer is located in a position higher than an opening surface of the first opening.   
     
     
         8 . The nitride semiconductor device according to  claim 7 ,
 wherein the lateral surface of the first opening is inclined relative to the bottom surface of the first opening,   an upper surface of the electron supply layer includes:
 a flat portion along the bottom surface of the first opening; 
 an inclined portion along the lateral surface of the first opening; and 
 an outer edge portion extending from an upper end of the inclined portion in a direction away from the flat portion; and 
   the lower surface of the second p-type nitride semiconductor layer continuously covers at least part of the flat portion, the inclined portion, and part of the outer edge portion.   
     
     
         9 . The nitride semiconductor device according to  claim 7 ,
 wherein in the planar view of the substrate, the second p-type nitride semiconductor layer overlaps with the first p-type nitride semiconductor layer.   
     
     
         10 . The nitride semiconductor device according to  claim 7  further comprising:
 a third p-type nitride semiconductor layer disposed between the gate electrode and the electron supply layer to be spaced from the second p-type nitride semiconductor layer. 
 
     
     
         11 . The nitride semiconductor device according to  claim 7  further comprising:
 an insulating film disposed between the gate electrode and the electron supply layer. 
 
     
     
         12 . The nitride semiconductor device according to  claim 7 ,
 wherein the electron supply layer includes an impurity region disposed in a position overlapping with the gate electrode in the planar view of the substrate.   
     
     
         13 . The nitride semiconductor device according to  claim 7 ,
 wherein a depressed portion is disposed in the electron supply layer in a position overlapping with the gate electrode in the planar view of the substrate.   
     
     
         14 . The nitride semiconductor device according to  claim 7 ,
 wherein a distance between the second p-type nitride semiconductor layer and the drain electrode is shorter than a distance between the first p-type nitride semiconductor layer and the drain electrode.   
     
     
         15 . The nitride semiconductor device according to  claim 7 ,
 wherein the second p-type nitride semiconductor layer includes a third opening that penetrates through the second p-type nitride semiconductor layer and reaches the electron supply layer, and   the second source electrode is in contact with the electron supply layer in a bottom surface of the third opening.

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