Operation method and semiconductor memory device

Abstract

In general, according to one embodiment, an operation method using a first latch circuit including: first and second inverters each includes an input terminal coupled to first and second nodes respectively, and an output terminal coupled to the second and first nodes, respectively, the operation method comprising: storing first and second data in the first and second node by setting the first and second inverters to a driven state, wherein the second data is inverted data of the first data; reading the first data from the first node to a bus coupled to the first latch circuit by setting the first and second inverters to an undriven state; writing the first data based on the second data to the first node from which the first data is read by setting the first inverter to the driven state; and driving the second inverter after the first data is written.

1 . An operation method using a first latch circuit including: a first inverter that includes an input terminal coupled to a first node and an output terminal coupled to a second node; and a second inverter that includes an input terminal coupled to the second node and an output terminal coupled to the first node,
 the operation method comprising:   storing first data in the first node and second data, which is inverted data of the first data, in the second node by setting the first inverter and the second inverter to a driven state;   reading the first data from the first node to a bus coupled to the first latch circuit by setting the first inverter and the second inverter to an undriven state;   writing the first data based on the second data to the first node from which the first data is read by setting the first inverter to the driven state; and   driving the second inverter after the first data is written.   
     
     
         2 . The operation method according to  claim 1 , further using a second latch circuit including: a third inverter that includes an input terminal coupled to a third node and an output terminal coupled to a fourth node; and a fourth inverter that includes an input terminal coupled to the fourth node and an output terminal coupled to the third node, wherein
 the storing further includes storing third data in the third node and fourth data, which is inverted data of the third data, in the fourth node by setting the third inverter and the fourth inverter to the driven state,   the reading further includes reading the third data from the third node to the bus by setting the third inverter and the fourth inverter to the undriven state.   
     
     
         3 . The operation method according to  claim 2 , further comprising:
 performing an AND operation on the first data and the third data read out to the bus, and outputting fifth data that is a result of the AND operation.   
     
     
         4 . The operation method according to  claim 3 , wherein the outputting includes outputting the fifth data to a sense circuit coupled to the bus. 
     
     
         5 . The operation method according to  claim 2 , wherein
 the writing further includes writing the third data based on the fourth data to the third node from which the third data is read by setting the third inverter to the driven state, and   the driving further includes driving the fourth inverter after the third data is written.   
     
     
         6 . The operation method according to  claim 3 , wherein the outputting includes outputting the fifth data to the third node. 
     
     
         7 . The operation method according to  claim 6 , wherein
 the writing further includes writing sixth data, which is inverted data of the fifth data, to the fourth node by setting the fourth inverter to driven state after the fifth data is output to the third node, and   the driving further includes driving the third inverter after the sixth data is written.   
     
     
         8 . A semiconductor memory device comprising:
 a sequencer;   a sense circuit;   a bus coupled to the sense circuit; and   a first latch circuit including: a first inverter that includes an input terminal coupled to a first node coupled to the bus and an output terminal coupled to a second node coupled to the bus; and a second inverter that includes an input terminal coupled to the second node and an output terminal coupled to the first node; wherein   the sequencer is configured to:
 drive the first inverter and the second inverter, store first data in the first node, and store second data, which is inverted data of the first data, in the second node; 
 set the first inverter and the second inverter to an undriven state, and read the first data from the first node to the bus; 
 drive the first inverter, and write the first data based on the second data to the first node from which the first data is read; and 
 drive the second inverter after the first data is written. 
   
     
     
         9 . The semiconductor memory device according to  claim 8 , further comprising:
 a second latch circuit including: a third inverter that includes an input terminal coupled to a third node coupled to the bus and an output terminal coupled to a fourth node coupled to the bus; and a fourth inverter that includes an input terminal coupled to the fourth node and an output terminal coupled to the third node, wherein   the sequencer is further configured to:   drive the third inverter and the fourth inverter, store third data in the third node, and store fourth data, which is inverted data of the third data, in the fourth node; and   set the third inverter and the fourth inverter to the undriven state, and read the third data from the third node to the bus.   
     
     
         10 . The semiconductor memory device according to  claim 9 , wherein the sequencer is further configured to perform an AND operation using the first data and the third data read out to the bus, and output fifth data, which is a result of the AND operation, to the sense circuit. 
     
     
         11 . The semiconductor memory device according to  claim 10 , wherein the sequencer is further configured to:
 drive the third inverter, and write the third data based on the fourth data to the third node from which the third data is read; and   drive the fourth inverter after the third data is written.   
     
     
         12 . The semiconductor memory device according to  claim 9 , wherein the sequencer is further configured to perform an AND operation on the first data and the third data read out to the bus, and output fifth data, which is a result of the AND operation, to the third node. 
     
     
         13 . The semiconductor memory device according to  claim 12 , wherein the sequencer is further configured to:
 drive the fourth inverter after the fifth data is output to the third node, and write sixth data, which is inverted data of the fifth data, to the fourth node, and   drive the third inverter after the sixth data is written.   
     
     
         14 . The semiconductor memory device according to  claim 13 , wherein a voltage of the fourth node is input to the sense circuit as a control signal. 
     
     
         15 . The semiconductor memory device according to  claim 13 , wherein a voltage of the third node is input to the sense circuit as a control signal. 
     
     
         16 . The semiconductor memory device according to  claim 8 , wherein the first latch circuit further includes:
 a first transistor including a first end coupled to the first node and a second end coupled to the bus;   a second transistor including a first end coupled to the second node and a second end coupled to the bus:   a third transistor and a fourth transistor each including a first end coupled to the first node, a second end, and a gate end coupled to the second node;   a fifth transistor and a sixth transistor each including a first end coupled to the second node, a second end, and a gate end coupled to the first node;   a seventh transistor including a first end coupled to the second end of the third transistor; and   an eighth transistor including a first end coupled to the second end of the fifth transistor, wherein the fifth transistor and the sixth transistor function as the first inverter,   the third transistor and the fourth transistor function as the second inverter,   the first transistor controls coupling between the first node and the bus,   the second transistor controls coupling between the second node and the bus,   the seventh transistor controls driving of the second inverter, and   the eighth transistor controls driving of the first inverter.   
     
     
         17 . The semiconductor memory device according to  claim 16 , wherein the second end of the fourth transistor and the second end of the sixth transistor are electrically decoupled from each other. 
     
     
         18 . The semiconductor memory device according to  claim 9 , wherein
 the second latch circuit further includes:
 a ninth transistor including a first end coupled to the third node and a second end coupled to the bus; 
 a tenth transistor including a first end coupled to the fourth node and a second end coupled to the bus; 
 an eleventh transistor and a twelfth transistor each including a first end coupled to the third node, a second end, and a gate end coupled to the fourth node; 
 a thirteenth transistor and a fourteenth transistor each including a first end coupled to the fourth node, a second end, and a gate end coupled to the third node; 
 a fifteenth transistor including a first end coupled to the second end of the eleventh transistor; and 
 a sixteenth transistor including a first end coupled to the second end of the thirteenth transistor, 
   the thirteenth transistor and the fourteenth transistor function as the third inverter,   the eleventh transistor and the twelfth transistor function as the fourth inverter,   the ninth transistor controls coupling between the third node and the bus,   the tenth transistor controls coupling between the fourth node and the bus,   the fifteenth transistor controls driving of the fourth inverter, and   the sixteenth transistor controls driving of the third inverter.   
     
     
         19 . The semiconductor memory device according to  claim 18 , wherein
 the first latch circuit further includes:
 a third transistor and a fourth transistor each including a first end coupled to the first node, a second end, and a gate end coupled to the second node; and 
 a fifth transistor and a sixth transistor each including a first end coupled to the second node, a second end, and a gate end coupled to the first node, 
   the fifth transistor and the sixth transistor function as the first inverter,   the third transistor and the fourth transistor function as the second inverter,   the second end of the fourth transistor, the second end of the sixth transistor, the second end of the twelfth transistor, and the second end of the fourteenth transistor are electrically decoupled from one another.   
     
     
         20 . The semiconductor memory device according to  claim 8 , wherein
 the semiconductor memory device is a NAND flash memory.