Hybrid gap controlled multi-clock cycle memory command protocol

Abstract

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

What is claimed is: 
     
         1 . Command decoder circuitry, comprising:
 gap select circuitry comprising:
 a latch, clocked by a clock signal, configured to receive a signal indicating a particular number of clock cycles between a first partial command at a first clock cycle and a second partial command at a second clock cycle; and 
 a SR latch coupled to an output of the latch and configured to generate a gap select signal; and 
   gap control circuitry comprising:
 a first D latch configured to generate a first signal based on a set of signals indicating a type of the first partial command; 
 a second D latch configured to generate a second signal based on the first signal; and 
 a select device configured to output a control signal selected from the first signal and the second signal based on the gap select signal, wherein the control signal is used to generate a gap having the particular number of clock cycles between the first partial command and the second partial command. 
   
     
     
         2 . The command decoder circuitry of  claim 1 , wherein the signal comprises a command/address (CA) signal. 
     
     
         3 . The command decoder circuitry of  claim 2 , wherein the CA signal is included in the first partial command. 
     
     
         4 . The command decoder circuitry of  claim 1 , wherein the first partial command comprises an activate-1 command (ACT-1) and the second partial command comprises an activate-2 command (ACT-2). 
     
     
         5 . The command decoder circuitry of  claim 1 , wherein the first D latch and the second D latch are clocked by an inverted signal of the clock signal. 
     
     
         6 . The command decoder circuitry of  claim 1 , wherein the set of signals comprise one or more command/address (CA) signals included in the first partial command. 
     
     
         7 . The command decoder circuitry of  claim 1 , wherein the selection device comprises a multiplexer. 
     
     
         8 . The command decoder circuitry of  claim 1 , wherein the control signal is used to block commands other than the second partial command during the second clock cycle. 
     
     
         9 . The command decoder circuitry of  claim 1 , wherein the particular number is equal to zero when the first signal is selected to be the control signal and equal to one when the second signal is selected to be the control signal. 
     
     
         10 . A system, comprising:
 gap select circuitry comprising:
 a plurality of latches, clocked by a clock signal, configured to receive respective signals indicating a particular number of clock cycles between a first partial command at a first clock cycle and a second partial command at a second clock cycle; and 
 respective SR latches coupled to respective outputs of the plurality of latches and configured to generate respective select signals, wherein the respective select signals are used to generate a gap select signal; and 
   gap control circuitry comprising:
 a set of D latches coupled in series, wherein a first D latch of the set of D latches is configured to generate a first signal based on a set of signals indicating a type of the first partial command, wherein each D latch other than the first D latch in the set of D latches is configured to generate a respective signal based on a respective output of a respective previous D latch; and 
 a select device configured to output a control signal selected from the first signal and the respective signal based on the gap select signal, wherein the control signal is used to generate a gap having the particular number of clock cycles between the first partial command and the second partial command. 
   
     
     
         11 . The system of  claim 10 , wherein the respective signals comprise command/address (CA) signals. 
     
     
         12 . The system of  claim 11 , wherein the CA signals are included in the first partial command. 
     
     
         13 . The system of  claim 10 , comprising gap determine circuitry configured to generate the gap select signal based on the respective select signals. 
     
     
         14 . The system of  claim 13 , wherein the gap determine circuitry comprises a number of AND gates. 
     
     
         15 . The system of  claim 10 , wherein the set of D latches are clocked by an inverted signal of the clock signal. 
     
     
         16 . The system of  claim 15 , wherein the set of signals comprises one or more command/address (CA) signals included in the first partial command. 
     
     
         17 . A device, comprising:
 a command interface configured to receive a plurality of command/address (CA) signals; and   command decoder circuitry comprising:
 gap select circuitry comprising:
 one or more latches, clocked by a clock signal, configured to receive respective CA signals of the plurality of CA signals, wherein the respective CA signals indicate a particular number of clock cycles between a first partial command at a first clock cycle and a second partial command at a second clock cycle; and 
 respective SR latches coupled to respective outputs of the one or more latches and configured to generate respective select signals used to generate a gap select signal; and 
 
 gap control circuitry comprising:
 a set of D latches coupled in series, wherein a first D latch of the set of D latches is configured to generate a first signal based on a set of CA signals of the plurality of CA signals, wherein each D latch other than the first D latch in the set of D latches is configured to generate a respective signal based on a respective output of a respective previous D latch; and 
 a select device configured to output a control signal selected from the first signal and the respective signal based on the gap select signal, wherein the control signal is used to generate a gap having a particular number of clock cycles between the first partial command and the second partial command. 
 
   
     
     
         18 . The device of  claim 17 , wherein the respective CA signals are included in the first partial command. 
     
     
         19 . The device of  claim 17 , wherein the set of D latches are clocked by an inverted signal of the clock signal. 
     
     
         20 . The device of  claim 17 , wherein the set of CA signals are included in the first partial command and indicate a type of the first partial command.