Multilayer electrode devices and method of making the same

Abstract

Semiconductor devices that include a replacement metallic gate electrode and a gate-level semiconductor structure can be formed on a seme semiconductor substrate by providing an etch-stop structure that prevents replacement of the gate-level semiconductor structure, and by replacing a sacrificial semiconductor gate electrode with the replacement metallic gate electrode. The gate-level semiconductor structure may include a semiconductor gate electrode of a field effect transistor, or a semiconductor material strip that can be employed as a resistor. In one embodiment, the etch-stop structure and an overlying sacrificial structure may be replaced with another replacement metallic gate electrode. In another embodiment, a silicide region may be formed on the semiconductor gate electrode.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a first field effect transistor comprising first source/drain regions located in a first portion of a semiconductor substrate, a first gate dielectric comprising a first metal oxide gate dielectric that comprises a first portion of a dielectric metal oxide material, and a first gate electrode comprising a metallic gate electrode contacting a top surface of the first gate dielectric; and   a second field effect transistor comprising second source/drain regions located in a second portion of the semiconductor substrate, a second gate dielectric, a second gate electrode comprising a doped semiconductor gate electrode, and a gate metal-semiconductor alloy region comprising an alloy of a first elemental metal and a semiconductor material of the doped semiconductor gate electrode.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a planarization dielectric layer laterally surrounding the first gate electrode and the second gate electrode and having a top surface within the horizontal plane containing a top surface of the metallic gate electrode. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the metallic gate electrode comprises at least one gate metallic liner each having a respective horizontally-extending portion and a respective tubular portion that vertically extends upward from a periphery of the respective horizontally-extending portion. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the second gate dielectric comprises:
 a silicon oxide gate dielectric; and   a second metal oxide gate dielectric that comprises a second portion of the dielectric metal oxide material.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein:
 sidewalls of the first metal oxide gate dielectric are vertically coincident with sidewalls of the metallic gate electrode;   sidewalls of the second metal oxide gate dielectric are vertically coincident with sidewalls of the doped semiconductor gate electrode; and   sidewalls of the silicon oxide gate dielectric are laterally offset outward relative to the sidewalls of the second metal oxide gate dielectric.   
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 a first dielectric gate spacer laterally surrounding the metallic gate electrode and having a first planar dielectric top surface; and   a second dielectric gate spacer laterally surrounding the doped semiconductor gate electrode and having a second planar dielectric top surface that is located within a same horizontal plane as the first planar dielectric top surface.   
     
     
         7 . The semiconductor structure of  claim 1 , wherein a topmost surface of the doped semiconductor gate electrode is located within a horizontal plane containing a top surface of the metallic gate electrode. 
     
     
         8 . The semiconductor structure of  claim 1 , further comprising a dielectric material layer contacting a top surface segment of the metallic gate electrode, contacting a top surface segment of the doped semiconductor gate electrode, and laterally surrounding the gate metal-semiconductor alloy region, wherein an interface between the dielectric material layer and the top surface segment of the metallic gate electrode is located within a same horizontal plane as an interface between the dielectric material layer and the top surface segment of the doped semiconductor gate electrode. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein a topmost surface of the doped semiconductor gate electrode is located below a horizontal plane containing a top surface of the metallic gate electrode, and wherein the gate metal-semiconductor alloy region comprises a metal silicide region. 
     
     
         10 . The semiconductor structure of  claim 1 , further comprising a gate cap dielectric overlying the doped semiconductor gate electrode, wherein a top surface of the metallic gate electrode is located within a horizontal plane including a top surface of the gate cap dielectric. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising a pair of source/drain metal-semiconductor alloy regions located on top of the second source/drain regions. 
     
     
         12 . The semiconductor structure of  claim 1 , further comprising a resistor structure that overlies an isolation dielectric layer and comprising:
 a semiconductor material strip having a same thickness as the doped semiconductor gate electrode; and   a pair of contact electrode metal-semiconductor alloy regions located on end portions of the semiconductor material strip.   
     
     
         13 . A method of forming a semiconductor structure, comprising:
 forming a first gate structure over a first portion of a semiconductor substrate and a second gate structure over a second portion of the semiconductor substrate, wherein the first gate structure comprises a first gate dielectric, a first semiconductor gate electrode, and a first sacrificial gate cap structure, and the second gate structure comprises a second gate dielectric, a second semiconductor gate electrode, and a second sacrificial gate cap structure;   forming a planarization dielectric layer around the first gate structure and the second gate structure;   forming a gate cavity by removing the first sacrificial gate cap structure and the first semiconductor gate electrode;   depositing at least one metallic material in the gate cavity and over the planarization dielectric layer; and   removing portions of the at least one metallic material, the second sacrificial gate cap structure, and an upper portion of the planarization dielectric layer from above a horizontal plane including a top surface of the second semiconductor gate electrode by performing a planarization process, wherein a remaining portion of the at least one metallic material in a lower portion of the gate cavity comprises a metallic gate electrode.   
     
     
         14 . The method of  claim 13 , further comprising:
 forming a dielectric material layer on the second semiconductor gate electrode, the metallic gate electrode, and a top surface of a remaining portion of the planarization dielectric layer after performing the planarization process;   forming an opening through the dielectric material layer over the second semiconductor gate electrode; and   forming a gate metal-semiconductor alloy region on the second semiconductor gate electrode within the opening through the dielectric material layer.   
     
     
         15 . The method of  claim 13 , further comprising:
 forming a first dielectric gate spacer around the first gate structure;   forming a second dielectric gate spacer around the second gate structure; and   removing top portions of the first dielectric gate spacer and the second dielectric gate spacer during formation of the planarization dielectric layer such that remaining portions of the first dielectric gate spacer and the second dielectric gate spacer comprise planar top surfaces that are formed within a horizontal plane containing a top surface of the planarization dielectric layer.   
     
     
         16 . The method of  claim 13 , wherein:
 the first gate dielectric comprises a first metal oxide gate dielectric that is formed directly on a top surface of the first portion of the semiconductor substrate; and   the second gate dielectric comprises a silicon oxide gate dielectric that is formed directly on a top surface of the second portion of the semiconductor substrate, and further comprises a second metal oxide gate dielectric that is formed on the silicon oxide gate dielectric and having a same material composition and a same thickness as the first metal oxide gate dielectric.   
     
     
         17 . A method of forming a semiconductor structure comprising:
 forming a first gate structure over a first portion of a semiconductor substrate and a second gate structure over a second portion of the semiconductor substrate, wherein the first gate structure comprises a first gate dielectric, a first semiconductor gate electrode, and a first sacrificial gate cap structure, and the second gate structure comprises a second gate dielectric, a second semiconductor gate electrode, a gate cap dielectric, and a second sacrificial gate cap structure;   forming an opening through the second sacrificial gate cap structure and the gate cap dielectric;   forming a gate metal-semiconductor alloy region on the second semiconductor gate electrode in the opening in the gate cap dielectric;   forming a planarization dielectric layer around the first gate structure and the second gate structure;   forming a gate cavity by removing the first sacrificial gate cap structure and the first semiconductor gate electrode;   depositing at least one metallic material in the gate cavity and over the planarization dielectric layer; and   removing portions of the at least one metallic material and the second sacrificial gate cap structure from above a horizontal plane including a top surface of the gate cap dielectric by performing a planarization process, wherein a remaining portion of the at least one metallic material in a lower portion of the gate cavity comprises a metallic gate electrode.   
     
     
         18 . The method of  claim 17 , further comprising forming source/drain metal-semiconductor alloy regions on the first portion of the semiconductor substrate and on the second portion of the semiconductor substrate concurrently with formation of the gate metal-semiconductor alloy region by depositing a metal layer and reacting the metal layer with a portion of the second semiconductor gate electrode, the first portion of the semiconductor substrate, and the second portion of the semiconductor substrate. 
     
     
         19 . The method of  claim 17 , further comprising:
 forming a first dielectric gate spacer around the first gate structure;   forming a second dielectric gate spacer around the second gate structure; and   removing top portions of the first dielectric gate spacer and the second dielectric gate spacer during formation of the planarization dielectric layer such that remaining portions of the first dielectric gate spacer and the second dielectric gate spacer comprise planar top surfaces that are formed within a horizontal plane containing a top surface of the planarization dielectric layer.   
     
     
         20 . The method of  claim 17 , further comprising:
 forming an isolation dielectric layer over a third portion of the semiconductor substrate;   forming a stack of a semiconductor resistor strip and a dielectric capping strip over the isolation dielectric layer, wherein the semiconductor resistor strip has a same thickness as the second semiconductor gate electrode, and the dielectric capping strip has a same material composition and a same thickness as the gate cap dielectric; and   forming a pair of contact metal-semiconductor alloy regions on end portions of the semiconductor resistor strip concurrently with formation of the gate metal-semiconductor alloy region by depositing a metal layer reacting the metal layer with a portion of the second semiconductor gate electrode and the end portions of the semiconductor resistor strip to form a resistor.