Semiconductor device and method of manufacturing same

Abstract

A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a carrier wafer comprising a membrane; and   an integrated circuit substrate bonded to the carrier wafer, the substrate comprising:
 at least one conductive component disposed within the substrate, the at least one conductive component interconnected with at least one integrated circuit component; 
 at least one sensing via disposed above at least one of the at least one conductive component and electrically coupled thereto; 
 at sensing electrode disposed above and electrically coupled to the at least one sensing via, the sensing electrode including a sidewall forming a wall of an isolation trench adjacent to the sensing electrode and sidewall thereof; and 
 a dielectric layer patterned on the sensing electrode and sidewall thereof having a thickness greater than two times a surface roughness of the sensing electrode; and 
   a cavity formed by the membrane positioned over the sensing electrode.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the isolation trench includes one or more additional dielectric layers disposed within. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the cavity inclusive of the at least one sensing electrode corresponds to a capacitive micromachined ultrasonic transducer unit. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the dielectric layer is an atomic layer deposited oxide. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the isolation trench is covered by one or more additional dielectric layers. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the dielectric layer lines the isolation trench and a top surface of the sensing electrode. 
     
     
         7 . An integrated circuit (IC) structure comprising:
 a semiconductor substrate;   a sensing electrode positioned on the semiconductor substrate, wherein the sensing electrode includes a sidewall forming a wall of an isolation trench adjacent the sensing electrode;   a dielectric layer patterned on the sensing electrode and sidewall thereof having a thickness greater than two times a surface roughness of the sensing electrode; and   a membrane positioned above the sensing electrode forming a cavity therein.   
     
     
         8 . The IC structure of  claim 7 , wherein the dielectric layer is an atomic layer deposited oxide. 
     
     
         9 . The IC structure of  claim 7 , wherein the sensing electrode is comprised of at least one of a sputtering deposited titanium or an ion metal plasma deposited titanium. 
     
     
         10 . The IC structure of  claim 7 , wherein the sensing electrode is electrically coupled to a conductive component of the integrated substrate through at least one sensing via. 
     
     
         11 . The IC structure of  claim 7 , wherein the dielectric layer lines the isolation trench and a top surface of the sensing electrode. 
     
     
         12 . The IC structure of  claim 11 , wherein the isolation trench includes at least one additional dielectric layer having a different construction from the dielectric layer. 
     
     
         13 . A semiconductor device, comprising:
 an integrated circuit substrate having a plurality of conductive components associated therewith;   at least one bottom dielectric layer formed on the integrated circuit substrate;   a plurality of sensing vias through the at least one bottom dielectric layer, the plurality of sensing vias interconnecting with at least one of the plurality of conductive components;   at least one sensing electrode patterned on the at least one bottom dielectric layer, wherein the at least one sensing electrode is in electrical communication with at least one of the plurality of sensing vias and the at least one sensing electrode has sidewalls forming walls of an isolation trench adjacent to the sensing electrode and sidewalls thereof;   at least one top dielectric layer formed subsequent to patterning of the at least one sensing electrode, the at least one top dielectric layer covering a top and the sidewalls of the at least one sensing electrode and the top dielectric layer patterned on each sensing electrode and sidewall thereof having a thickness greater than two times a surface roughness of the sensing electrode;   at least one cavity on the integrated circuit substrate, wherein the at least one sensing electrode is disposed therein; and   a carrier wafer bonded to the integrated substrate.   
     
     
         14 . The device of  claim 13 , wherein the carrier wafer includes at least one membrane disposed above the at least one cavity. 
     
     
         15 . The device of  claim 13 , wherein the at least one top dielectric layer includes one or more additional dielectric layers. 
     
     
         16 . The device of  claim 15 , wherein the at least one top dielectric layer is an atomic layer deposited oxide. 
     
     
         17 . The device of  claim 13 , wherein the at least one sensing electrode is a metal deposited via sputtering or ion metal plasma deposition. 
     
     
         18 . The device of  claim 13 , wherein the at least one sensing electrode is a bottom electrode of a capacitive micromachined ultrasonic transducer unit. 
     
     
         19 . The device of  claim 13 , wherein the plurality of conductive components are of a first conductive material and the plurality of sensing vias are of a second conductive material, the first and second conductive materials distinct therefrom. 
     
     
         20 . The device of  claim 13 , wherein the isolation trench is covered by the at least one top dielectric layer.