Trench-based super junction structures via sidewall doping

Abstract

A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. A trench may be etched for both a P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio to fill the trench. The P-type material may then be formed by doping the sidewalls of the trench for a P-type layer that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.

What is claimed is: 
     
         1 . A method of forming a super junction device, the method comprising:
 forming a first N-type material on a substrate;   etching a trench in the first N-type material, wherein the trench forms at least a first N-type region from the first N-type material;   causing a sidewall of the trench comprising the first N-type region to be doped with a P-type dopant to form a P-type region in the first N-type region; and   filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region.   
     
     
         2 . The method of  claim 1 , wherein causing the sidewall of the first N-type region in the trench to be doped with the P-type dopant also causes a bottom of the trench to be doped with the P-type dopant. 
     
     
         3 . The method of  claim 1 , wherein etching the trench in the first N-type material causes the trench to extend down from a top surface of the first N-type material, and a bottom of the trench comprises at least a portion of the first N-type material between the bottom of the trench and the substrate such that the substrate is not exposed at the bottom of the trench. 
     
     
         4 . The method of  claim 1 , further comprising forming a protective oxide layer on the P-type region and a bottom of the trench. 
     
     
         5 . The method of  claim 4 , wherein the protective oxide layer is between about 5 nm and about 15 nm thick and is formed conformally inside of the trench. 
     
     
         6 . The method of  claim 1 , further comprising performing a directional etch downward into the trench to remove a P-doped region at a bottom of the trench without removing the P-type region along the sidewall of the trench. 
     
     
         7 . The method of  claim 6 , further comprising removing a protective oxide layer on the P-type region after performing the directional etch, wherein the directional etch also removes a protective oxide layer on the bottom of the trench. 
     
     
         8 . The method of  claim 6 , wherein the directional etch does not expose a top surface of the substrate at a bottom of the trench. 
     
     
         9 . A method of forming a super junction device, the method comprising:
 etching a trench in a first N-type material on a substrate, wherein the trench forms at least a first N-type region from the first N-type material;   forming a P-doped layer on a sidewall of the trench comprising the first N-type region, wherein the P-doped layer comprises a P-type dopant;   annealing the P-doped layer sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region; and   filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region.   
     
     
         10 . The method of  claim 9 , wherein the P-doped layer comprises boron-doped silicon oxide formed using a deposition operation. 
     
     
         11 . The method of  claim 9 , wherein the P-doped layer comprises boron-doped silicon nitride formed using a deposition operation. 
     
     
         12 . The method of  claim 9 , wherein the P-doped layer comprises borophosphosilicate (BPSG) glass. 
     
     
         13 . The method of  claim 9 , wherein the P-doped layer is between about 50 nm and 150 nm thick. 
     
     
         14 . The method of  claim 9 , wherein annealing the doped layer comprises applying a temperature that is between about 700° C. and about 1100° C. 
     
     
         15 . The method of  claim 9 , wherein the P-type dopant diffuses into the first N-type region to a depth of between about 100 nm and about 200 nm. 
     
     
         16 . The method of  claim 9 , wherein the P-type dopant diffuses into the first N-type region to a concentration of between about 5e16 atoms/cm 3  and about 5e17 atoms/cm 3 . 
     
     
         17 . A method of forming a super junction device, the method comprising:
 etching a trench in a first N-type material, wherein the trench forms at least a first N-type region in the first N-type material;   performing a plasma doping (PLAD) operation on a sidewall of the trench comprising the first N-type region, wherein the PLAD operation dopes the sidewall with a P-type dopant;   annealing the sidewall sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region; and   filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region.   
     
     
         18 . The method of  claim 17 , wherein a height of the P-type region is greater than or about 70 μm. 
     
     
         19 . The method of  claim 17 , wherein a combined width of the P-type region and the second N-type region is less than or about 4 μm. 
     
     
         20 . The method of  claim 17 , wherein an aspect ratio of an area occupied by second the N-type region and the P-type region is less than or about 20.