Semiconductor device and method for fabricating the same

Abstract

The embodiments of the present disclosure are directed to a semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device, and the semiconductor device may include a plurality of nano sheets that are vertically stacked; a first conductive line coupled in common to first edges of the nano sheets, the first conductive line being oriented vertically; a plurality of data storage elements, each data storage element being coupled to second edges of the nano sheets; a plurality of second conductive lines, each second conductive line surrounding the nano sheets and being oriented horizontally; and a plurality of inter-cell dielectric layers disposed between the second conductive lines and each including an air gap.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of nano sheets that are vertically stacked;   a first conductive line coupled in common to first edges of the nano sheets, the first conductive line being oriented vertically;   a plurality of data storage elements, each data storage element being coupled to second edges of the nano sheets;   a plurality of second conductive lines, each second conductive line surrounding the nano sheets and being oriented horizontally; and   a plurality of inter-cell dielectric layers disposed between the second conductive lines and each including an air gap.   
     
     
         2 . The semiconductor device of  claim 1 , wherein each of the inter-cell dielectric layers includes an air gap forming layer in which the air gap is embedded. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the air gap forming layer includes silicon oxide. 
     
     
         4 . The semiconductor device of  claim 1 , wherein each of the inter-cell dielectric layers further includes silicon carbon oxide in contact with the first conductive line. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 a first spacer disposed between each of the inter-cell dielectric layers and each of the data storage elements; and   a second spacer disposed between each of the inter-cell dielectric layers and the first conductive line.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the first spacer has a shape surrounding the nano sheets at the same horizontal level and covering a side surface of each of the inter-cell dielectric layers. 
     
     
         7 . The semiconductor device of  claim 1 , wherein each of the nano sheets includes a flat plate-shaped sheet in contact with the first conductive line and a fan-shaped sheet in contact with each of the data storage elements. 
     
     
         8 . The semiconductor device of  claim 7 , wherein each of the nano sheets includes first and second doped regions spaced apart from each other in a second direction and a channel between the first doped region and the second doped region, and wherein the first doped region and the channel are disposed in the flat plate-shaped sheet, and the second doped region is disposed in the fan-shaped sheet. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 first contact nodes disposed between the nano sheets and the first conductive line; and   second contact nodes disposed between the nano sheets and the data storage elements.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the second contact nodes each include a selective epitaxial growth layer. 
     
     
         11 . A method for fabricating a semiconductor device, the method comprising:
 forming nano sheet target layers that are vertically stacked and spaced apart from each other over a substrate;   trimming first portions of the nano sheet target layers and forming flat plate-shaped sheets;   forming a first spacer layer defining inner spaces in upper and lower portions of the flat plate-shaped sheets;   forming air gap target layers that fill the inner spaces;   forming strip barrier layers and strip paths between the strip barrier layers at entrances of the inner spaces;   removing the air gap target layers through the strip paths and forming initial air gaps;   forming air gap forming layers filling the initial air gaps and in which air gaps are embedded;   horizontally recessing the first spacer layer to form a first spacer covering side surfaces of the air gap forming layers and surrounding recesses exposing the upper and lower portions of the flat plate-shaped sheets; and   forming horizontal conductive lines filling the surrounding recesses and being disposed between the air gap forming layers.   
     
     
         12 . The method of  claim 11 , wherein the air gap forming layers each include a dielectric material. 
     
     
         13 . The method of  claim 11 , wherein the air gap forming layers each include silicon oxide. 
     
     
         14 . The method of  claim 11 , wherein the air gap target layers each include polysilicon or silicon oxide. 
     
     
         15 . The method of  claim 11 , wherein the strip barrier layers are selectively deposited from an exposed surface of the first spacer layer. 
     
     
         16 . The method of  claim 11 , wherein the strip barrier layers each include silicon carbon oxide, and the first spacer layer includes silicon nitride. 
     
     
         17 . The method of  claim 11 , wherein the nano sheet target layers each include monocrystalline silicon. 
     
     
         18 . The method of  claim 11 , further comprising:
 forming first contact nodes coupled to the flat plate-shaped sheets;   forming a vertical conductive line coupled in common to the first contact nodes;   horizontally recessing second portions of the nano sheet target layers and forming fan-shaped sheets;   selectively growing the second contact nodes on side surfaces of the fan-shaped sheets; and   forming data storage elements coupled to the second contact nodes.   
     
     
         19 . The method of  claim 18 , wherein selectively growing the second contact nodes on the side surfaces of the fan-shaped sheets includes growing a doped silicon layer through a selective epitaxial growth. 
     
     
         20 . The method of  claim 11 , wherein the horizontal conductive lines extend while surrounding the flat plate-shaped sheets disposed at the same horizontal level, and each of the air gap forming layers is disposed between the horizontal conductive lines that are vertically stacked.