Flexible preamble execution in graphics processing

Abstract

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of set of draw calls, wherein each of the set of draw calls includes a shader preamble. The apparatus may also obtain an indication of a division of each shader preamble for each of the set of draw calls into a plurality of shader preamble sections. Further, the apparatus may execute, based on the division of each shader preamble, each of the plurality of shader preamble sections for each of the set of draw calls.

What is claimed is: 
     
         1 . An apparatus for graphics processing, comprising:
 at least one memory; and   at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to:
 obtain an indication of set of draw calls, wherein each of the set of draw calls includes a shader preamble; 
 obtain an indication of a division of each shader preamble for each of the set of draw calls into a plurality of shader preamble sections; and 
 execute, based on the division of each shader preamble, each of the plurality of shader preamble sections for each of the set of draw calls. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the plurality of shader preamble sections includes at least one of: a high level sequencer (HLSQ) preamble section, a streaming processor (SP) preamble section, or a work group (WG) preamble section. 
     
     
         3 . The apparatus of  claim 2 , wherein to execute each of the plurality of shader preamble sections, the at least one processor, individually or in any combination, is configured to:
 execute the HLSQ preamble section at an HLSQ of a graphics processing unit (GPU);   execute the SP preamble section at an SP of the GPU; and   execute the WG preamble section per WG at the SP of the GPU.   
     
     
         4 . The apparatus of  claim 2 , wherein each of the plurality of shader preamble sections is adjacent to a shader preamble start (SHPS) instruction and a shader preamble end (SHPE) instruction. 
     
     
         5 . The apparatus of  claim 1 , wherein the at least one processor, individually or in any combination, is further configured to:
 perform a main shader execution for each of the set of draw calls based on the execution of each of the plurality of shader preamble sections for each of the set of draw calls.   
     
     
         6 . The apparatus of  claim 1 , wherein to execute each of the plurality of shader preamble sections, the at least one processor, individually or in any combination, is configured to:
 execute each of the plurality of shader preamble sections at a high level sequencer (HLSQ) of a graphics processing unit (GPU) or a streaming processor (SP) of the GPU.   
     
     
         7 . The apparatus of  claim 6 , wherein to execute each of the plurality of shader preamble sections, the at least one processor, individually or in any combination, is configured to:
 execute a first preamble section of the plurality of shader preamble sections at the HLSQ;   execute a second preamble section of the plurality of shader preamble sections at the SP; and   execute a third preamble section of the plurality of shader preamble sections once per work group at the SP.   
     
     
         8 . The apparatus of  claim 7 , wherein the first preamble section of the plurality of shader preamble sections corresponds to a first bit associated with a context register, the second preamble section of the plurality of shader preamble sections corresponds to a second bit associated with the context register, and the third preamble section of the plurality of shader preamble sections corresponds to a third bit associated with the context register. 
     
     
         9 . The apparatus of  claim 7 , wherein to execute the first preamble section at the HLSQ, the at least one processor, individually or in any combination, is configured to:
 execute the first preamble section at the HLSQ if an enable bit is set that corresponds to the first preamble section.   
     
     
         10 . The apparatus of  claim 7 , wherein to execute each of the plurality of shader preamble sections at the HLSQ or the SP, the at least one processor, individually or in any combination, is configured to:
 execute the first preamble section at the HLSQ; and   refrain from executing the second preamble section and the third preamble section at the HLSQ.   
     
     
         11 . The apparatus of  claim 7 , wherein to execute the second preamble section at the SP, the at least one processor, individually or in any combination, is configured to:
 execute the second preamble section at the SP if an enable bit is set that corresponds to the second preamble section.   
     
     
         12 . The apparatus of  claim 7 , wherein to execute the second preamble section at the SP, the at least one processor, individually or in any combination, is configured to:
 execute the second preamble section at the SP; and   remove shader code that corresponds to the second preamble section after the execution of the second preamble section at the SP.   
     
     
         13 . The apparatus of  claim 7 , wherein to execute the third preamble section once per work group at the SP, the at least one processor, individually or in any combination, is configured to:
 execute the third preamble section once per work group at the SP during a first wave of a plurality of waves of a first work group; and   refrain from executing the third preamble section during remaining waves of the plurality of waves of the first work group.   
     
     
         14 . The apparatus of  claim 1 , wherein to obtain the indication of the division of each shader preamble for each of the set of draw calls into the plurality of shader preamble sections, the at least one processor, individually or in any combination, is configured to:
 receive, from a compiler at a central processing unit (CPU), the indication of the division of each shader preamble for each of the set of draw calls into the plurality of shader preamble sections.   
     
     
         15 . The apparatus of  claim 1 , wherein to obtain the indication of the division of each shader preamble for each of the set of draw calls into the plurality of shader preamble sections comprises:
 determine, at a graphics processing unit (GPU), the division of each shader preamble for each of the set of draw calls into the plurality of shader preamble sections.   
     
     
         16 . The apparatus of  claim 1 , wherein each of the set of draw calls includes a set of work groups (WGs), and wherein to obtain the indication of the set of draw calls, the at least one processor, individually or in any combination, is configured to:
 obtain the indication of the set of draw calls including the set of WGs.   
     
     
         17 . The apparatus of  claim 1 , wherein to obtain the indication of the set of draw calls, the at least one processor, individually or in any combination, is configured to:
 receive the indication of the set of draw calls; or   determine the set of draw calls.   
     
     
         18 . The apparatus of  claim 1 , wherein the at least one processor, individually or in any combination, is further configured to:
 output an indication of the execution of the plurality of shader preamble sections for each of the set of draw calls.   
     
     
         19 . A method of graphics processing, comprising:
 obtaining an indication of set of draw calls, wherein each of the set of draw calls includes a shader preamble;   obtaining an indication of a division of each shader preamble for each of the set of draw calls into a plurality of shader preamble sections; and   executing, based on the division of each shader preamble, each of the plurality of shader preamble sections for each of the set of draw calls.   
     
     
         20 . An apparatus for graphics processing, comprising:
 at least one memory; and   at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to:
 obtain an indication of set of draw calls, wherein each of the set of draw calls includes a shader preamble; 
 determine a division of each shader preamble for each of the set of draw calls into a plurality of shader preamble sections; and 
 output, based on the division of each shader preamble, an indication of the division of each shader preamble for each of the set of draw calls into the plurality of shader preamble sections.