System and method for a silicon photonic bridge in an electronic package

Abstract

A silicon photonic bridge and method of manufacturing an integrated circuit semiconductor package may be provided. The system may include an interposer layer formed from a combination of organic and inorganic materials. The silicon photonic bridge may be embedded within the interposer layer. The silicon photonic bridge may include an electrical integrated circuit (IC) configured to process electrical signals and drive the photonic IC (PIC), and a PIC configured to process optical signals, an optical connector element(s) configured to interface the PIC with fiber and a silicon bridge configured to interface between an ASIC integrated on top of the interposer with the EIC. A silicon photonic bridge may be electrically and optically enabled to convert the electrical signal from the ASIC above the interposer to an optical signal going into fiber, and vice versa. Through-silicon vias (TSVs) may extend through the optical engine.

1 . A system, comprising: 
 a layer formed from one or more of organic materials or inorganic materials, wherein the layer is one or more of an interposer layer or a substrate layer;   a silicon photonic bridge embedded within the layer, wherein the silicon photonic bridge comprises: 
 a photonic integrated circuit (PIC) configured to process optical signals; 
 an electrical integrated circuit (EIC) configured to process electrical signals and drive the PIC; and 
 a silicon bridge electrically coupled to the EIC to facilitate connection of electrical signals to the EIC. 
   
     
     
         2 . The system of  claim 1 , further comprising a plurality of electrical vias extending through the PIC, the electrical vias configured to provide one or more of power, ground, or signaling connections to the one or more of the EIC or PIC. 
     
     
         3 . The system of  claim 1 , wherein the silicon photonic bridge is integrated into the layer and provides an interconnection between an application specific integrated circuit (ASIC) integrated on top of the layer and an optical fiber output within the system. 
     
     
         4 . The system of  claim 3 , wherein the silicon photonic bridge is configured to support a protocol-agnostic communication interface between the ASIC and the optical fiber output. 
     
     
         5 . The system of  claim 1 , wherein the silicon photonic bridge includes a vertical light path integrated into the layer, wherein the vertical light path facilitates transmitting and receiving of optical signals through the layer without interference from surrounding electronic components. 
     
     
         6 . The system of  claim 1 , wherein the layer is compatible with 2.5D semiconductor packaging processes. 
     
     
         7 . The system of  claim 1 , wherein the silicon photonic bridge is configured to facilitate data transfer rates by using one or more wavelengths of light within the PIC. 
     
     
         8 . The system of  claim 1 , wherein an optical engine is configured to support conversion of electrical signals from different protocols into corresponding optical signals within the silicon photonic bridge. 
     
     
         9 . The system of  claim 1 , wherein a top surface of the layer facilitates one or more of a hybrid or fusion bonding interface with an alignment of 1 micron or less to facilitate adhesion of a collimator to the silicon photonic bridge to facilitate vertical optical coupling. 
     
     
         10 . The system of  claim 1 , wherein the silicon photonic bridge is configured to optimize thermal extraction from the layer.  
     
     
         11 . The system of  claim 1 , wherein the silicon photonic bridge is configured to aggregate a plurality of lower speeds channels to a single higher speed channel using a die-to-die interface converted to optical standard protocols.  
     
     
         12 . A method of manufacturing a semiconductor package comprising a silicon photonic bridge embedded within one or more of an interposer layer or a substrate, the method comprising: 
 providing one or more of the interposer layer or the substrate formed from one or more of organic materials or inorganic materials;   forming a silicon photonic bridge comprising: an electrical integrated circuit (EIC), a photonic IC (PIC), optical coupling features, and a silicon bridge, wherein the silicon photonic bridge is configured to convert electrical signals into optical signals and convert optical signals into electrical signals;   embedding the silicon photonic bridge into the one or more of the interposer layer or the substrate; and   integrating a vertical light path within the interposer layer, allowing for optical signals to be transmitted and received through the interposer layer.   
     
     
         13 . The method of  claim 12 , wherein the silicon photonic bridge comprises a plurality of electrical vias extending through the silicon photonic bridge, wherein the electrical vias are configured to provide one or more of power, ground, or signaling connections. 
     
     
         14 . The method of  claim 12 , further comprising: 
 attaching a system-on-chip (SoC) to the interposer layer or the substrate via the silicon bridge embedded in the silicon photonic bridge.   
     
     
         15 . The method of  claim 12 , wherein the operation of embedding the silicon photonic bridge into the one or more of the interposer layer or the substrate further comprises aligning the silicon bridge to facilitate accurate signal transmission to an application specific integrated circuit (ASIC) placed above the interposer. 
     
     
         16 . The method of  claim 12 , wherein the operation of forming the silicon photonic bridge comprises using one or more of a hybrid bonding process or a fusion bonding process with an alignment of 1 microns or less. 
     
     
         17 . The method of  claim 12 , wherein the testing operation includes both electrical probing and optical probing to validate the functionality of the silicon photonic bridge and the interposer. 
     
     
         18 . The method of  claim 12 , further comprising the operation of adding a heat sink to the semiconductor package to dissipate heat from the silicon photonic bridge and other ASICs during operation. 
     
     
         19 . The method of  claim 12 , further comprising the operation of integrating one or more of a collimator or mechanical alignment element into the semiconductor package to facilitate optical signal transmission and top-down testing. 
     
     
         20 . The method of  claim 12 , wherein the method is compatible with one or more manufacturing standards set by the Joint Electron Device Engineering Council (JEDEC), Telcordia, or a combination thereof.