Semiconductor device and method for operating the same

Abstract

A semiconductor device including one or more memory cells and a method for operating the same are disclosed. Each of the memory cells includes a first transistor configured to write data, a second transistor configured to store the data, and a third transistor configured to refresh the data. The memory cell includes a first transistor including a first gate connected to a write word line and one terminal connected to a storage node, a second transistor including a second gate connected to the storage node and one terminal connected to a read word line and a third transistor including a third gate connected to the read word line and one terminal connected to a read bit line.

What is claimed is: 
     
         1 . A memory cell comprising:
 a first gate disposed to contact a write word line;   a second gate disposed below the first gate and disposed over a read bit line, the second gate penetrating a read word line;   a third gate spaced apart from the second gate and disposed over the read bit line;   a first interconnect structure disposed to partially contact the second gate, and the first interconnect structure being penetrated by the third gate; and   a second interconnect structure disposed to contact the read word line and the third gate.   
     
     
         2 . The memory cell according to  claim 1 , wherein:
 the first gate is disposed to penetrate a write bit line;   the write word line and the read word line are disposed to extend in a first direction; and   the write bit line and the read bit line are disposed to extend in a second direction different from the first direction.   
     
     
         3 . The memory cell according to  claim 1 , wherein the first interconnect structure includes:
 a first horizontal interconnect layer disposed to contact the second gate;   a second horizontal interconnect layer disposed to be penetrated by the third gate; and   a vertical interconnect layer disposed to contact the first horizontal interconnect layer and the second horizontal interconnect layer.   
     
     
         4 . The memory cell according to  claim 3 , wherein:
 a first channel layer is disposed to contact a side surface and a bottom surface of the first gate and disposed to contact the write bit line;   a second channel layer is disposed to contact a side surface and a bottom surface of the second gate and disposed to contact the read word line; and   a third channel layer is disposed to contact a side surface and a bottom surface of the third gate and disposed to contact the second horizontal interconnect layer.   
     
     
         5 . The memory cell according to  claim 4 , wherein
 each of the first to third channel layers includes an oxide semiconductor.   
     
     
         6 . The memory cell according to  claim 5 , wherein
 the oxide semiconductor includes at least one of In—Sn—Ga—Zn—O, In—Ga—Zn—O, In—Al—Zn—O, Sn—Ga—Zn—O, Al—Ga—Zn—O, Sn—Al—Zn—O, In—Zn—O, Sn—Zn—O, Al—Zn—O, Zn—Mg—O, Sn—Mg—O, In—Mg—O, and In—Ga—O.   
     
     
         7 . The memory cell according to  claim 2 , wherein:
 each of the first to third gates is disposed to extend in a third direction perpendicular to the first direction; and   the second gate is disposed spaced apart from the first gate in the third direction, and a height of the second gate in the third direction is higher than a height of the third gate in the third direction.   
     
     
         8 . A semiconductor device comprising:
 a first transistor including a first gate connected to a write word line and one terminal connected to a storage node;   a second transistor including a second gate connected to the storage node and one terminal connected to a read word line; and   a third transistor including a third gate connected to the read word line and one terminal connected to a read bit line.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein:
 the second transistor includes another terminal connected to the read bit line; and   the third transistor includes another terminal connected to the storage node.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein
 the first transistor includes another terminal connected to a write bit line.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein:
 when a first word line signal applied to the write word line has a high level, the first transistor is turned on; and   when the first word line signal has a low level, the first transistor is turned off.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein:
 when the first word line signal has a high level and a first bit line signal applied to the write bit line has a high level, data corresponding to “1” is stored in the storage node; and   when the first word line signal has a high level and the first bit line signal has a low level, data corresponding to “0” is stored in the storage node.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein:
 when the data corresponding to “1” is stored in the storage node, the second transistor is turned on; and   when the data corresponding to “0” is stored in the storage node, the second transistor is turned off.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein:
 when a second word line signal applied to the read word line has a high level and the second transistor is turned on, a second bit line signal having a high level is applied to the read bit line; and   when the second word line signal applied to the read word line has a low level and the second transistor is turned off, the second bit line signal having a low level is applied to the read bit line.   
     
     
         15 . The semiconductor device according to  claim 13 , wherein:
 the read word line is configured to receive a second word line signal having a high level to turn on the third transistor; and   the third transistor is configured to refresh data stored in the storage node.   
     
     
         16 . A method for operating a semiconductor device, the method comprising:
 applying a first word line signal to a gate of a first transistor;   storing data corresponding to a level of a first bit line signal applied to one terminal of the first transistor in a storage node connected to a second transistor;   applying a second word line signal to one terminal of the second transistor;   outputting a second bit line signal corresponding to the data to another terminal of the second transistor;   applying the second bit line signal to one terminal of a third transistor; and   refreshing the data stored in the storage node.   
     
     
         17 . The method according to  claim 16 , wherein:
 when the first word line signal has a high level, the first transistor is turned on; and   when the first word line signal has a low level, the first transistor is turned off.   
     
     
         18 . The method according to  claim 16 , wherein:
 when the first bit line signal has a high level, the data is “1”; and   when the first bit line signal has a low level, the data is “0”.   
     
     
         19 . The method according to  claim 18 , wherein:
 when the data is “1”, the second transistor is turned on; and   when the data is “0”, the second transistor is turned off.   
     
     
         20 . The method according to  claim 18 , wherein:
 when the data is “1”, the second bit line signal has a high level; and   when the data is “0”, the second bit line signal has a low level.   
     
     
         21 . The method according to  claim 20 , wherein:
 when the second bit line signal is at the high level, the data stored in the storage node is refreshed to “1”; and   when the second bit line signal is at the low level, the data stored in the storage node is refreshed to “0”.