Memory device and memory system

Abstract

A memory device includes a memory string. The memory string includes first switch elements and second switch elements. The second switch elements are arranged alternately and coupled in series with the first switch elements. When the memory string has a first conductance, each switch element of the first switch elements has a first threshold voltage level and each switch element of the second switch elements has a second threshold voltage level, when the memory string has a second conductance, each switch element of a first portion of the first switch elements has the second threshold voltage level and each switch element of a second portion of the second switch elements has the first threshold voltage level, the first conductance is smaller than the second conductance, and the first threshold voltage level is larger than the second threshold voltage level.

What is claimed is: 
     
         1 . A memory device, comprising a memory string, the memory string comprising:
 a plurality of first switch elements; and   a plurality of second switch elements arranged alternately and coupled in series with the plurality of first switch elements,   wherein when the memory string has a first conductance, each switch element of the plurality of first switch elements has a first threshold voltage level and each switch element of the plurality of second switch elements has a second threshold voltage level,   when the memory string has a second conductance, each switch element of a first portion of the plurality of first switch elements has the second threshold voltage level and each switch element of a second portion of the plurality of second switch elements has the first threshold voltage level,   the first conductance is smaller than the second conductance, and   the first threshold voltage level is larger than the second threshold voltage level.   
     
     
         2 . The memory device of  claim 1 , wherein when the memory string has a third conductance, one of the plurality of first switch elements has a third threshold voltage level,
 the second conductance is larger than the third conductance, and   the third threshold voltage level is larger than the first threshold voltage level.   
     
     
         3 . The memory device of  claim 1 , wherein when the memory string has a third conductance, each switch element of a third portion of the plurality of first switch elements has the second threshold voltage level, and each switch element of a fourth portion of the plurality of second switch elements has the first threshold voltage level,
 the third conductance is larger than the second conductance, and   a quantity of switch elements of the third portion is larger than a quantity of switch elements of the first portion, and   a quantity of switch elements of the fourth portion is larger than a quantity of switch elements of the second portion.   
     
     
         4 . The memory device of  claim 1 , wherein when the memory string has a third conductance, a third switch element of the plurality of first switch elements has a third threshold voltage level,
 the third conductance is larger than the second conductance, and   the third threshold voltage level is larger than the first threshold voltage level.   
     
     
         5 . The memory device of  claim 4 , wherein when the memory string has a fourth conductance, the third switch element has a fourth threshold voltage level,
 the fourth conductance is larger than the third conductance,   the first threshold voltage level is larger than the fourth threshold voltage level, and   the second threshold voltage level is smaller than the fourth threshold voltage level.   
     
     
         6 . A memory device, comprising:
 a first memory string configured to receive a plurality of first word line signals; and   a second memory string coupled in parallel with the first memory string, and configured to receive a plurality of second word line signals,   wherein the plurality of first word line signals and the plurality of second word line signals correspond to an input bit,   when the input bit has a first encode value, each of a first portion of the plurality of first word line signals has a first voltage level, each of a second portion of the plurality of first word line signals has a second voltage level, and each of the plurality of second word line signals has the first voltage level,   when the input bit has a second encode value, each of a third portion of the plurality of second word line signals has the first voltage level, each of a fourth portion of the plurality of second word line signals has the second voltage level, and each of the plurality of first word line signals has the first voltage level, and   the first encode value is different from the second encode value.   
     
     
         7 . The memory device of  claim 6 , wherein the second voltage level is larger than the first voltage level. 
     
     
         8 . The memory device of  claim 6 , wherein when the input bit has a wildcard encode value, each of the plurality of first word line signals and the plurality of second word line signals has the first voltage level. 
     
     
         9 . The memory device of  claim 8 , wherein when the input bit has the first encode value, the input bit has a first logic value,
 when the input bit has the wildcard encode value, the input bit has a second logic value larger than the first logic value, and   the input bit has the second encode value, the input bit has a third logic value larger than the second logic value.   
     
     
         10 . The memory device of  claim 6 , wherein the first memory string and the second memory string are further configured to store a store bit,
 when the store bit has a first logic value, the first memory string and the second memory string have a first conductance and a second conductance, respectively,   when the store bit has a second logic value, the first memory string and the second memory string have the second conductance and the first conductance, respectively, and   the second conductance is larger than the first conductance.   
     
     
         11 . The memory device of  claim 10 , wherein the second conductance is proportional to a square of a difference between the second logic value and the first logic value. 
     
     
         12 . The memory device of  claim 10 , wherein when the store bit has a third logic value, the first memory string and the second memory string have a third conductance and a fourth conductance, respectively,
 the third conductance is proportional to a square of a difference between the third logic value and the first logic value, and   the fourth conductance is proportional to a square of a difference between the third logic value and the second logic value.   
     
     
         13 . The memory device of  claim 12 , wherein when the store bit has a fourth logic value, the first memory string and the second memory string have a fifth conductance and a sixth conductance, respectively,
 the fifth conductance is proportional to a square of a difference between the fourth logic value and the first logic value, and   the sixth conductance is proportional to a square of a difference between the fourth logic value and the second logic value.   
     
     
         14 . The memory device of  claim 13 , wherein a difference between the fourth logic value and the third logic value is equal to the difference between the third logic value and the first logic value. 
     
     
         15 . The memory device of  claim 10 , wherein the first memory string and the second memory string are further configured to generate a first string current signal and a second string current signal,
 when the input bit has the first encode value, a current level of the first string current signal is proportional a square of a difference between a logic value of the input bit and a logic value of the store bit, and   when the input bit has the second encode value, a current level of the second string current signal is proportional the square of the difference between the logic value of the input bit and the logic value of the store bit.   
     
     
         16 . The memory device of  claim 15 , wherein
 when the input bit has the first encode value, the second string current signal has a zero current level, and   when the input bit has the second encode value, the first string current signal has the zero current level.   
     
     
         17 . The memory device of  claim 15 , wherein when the input bit has a wildcard encode value, each of the first string current signal and the second string current signal has a zero current level. 
     
     
         18 . A memory system, comprising
 a plurality of memory blocks configured to receive a plurality of string select line signals, respectively; and   a sensing device configured to receive a plurality of bit line signals from the plurality of memory blocks,   wherein the plurality of memory blocks comprises a plurality of first memory string pairs,   the plurality of first memory string pairs are configured to store a plurality of first store bits, respectively, and   the plurality of first memory string pairs are configured to compare the plurality of first store bits and a plurality of input bits, to generate a first bit line signal of the plurality of bit line signals.   
     
     
         19 . The memory system of  claim 18 , wherein the plurality of memory blocks further comprises a plurality of second memory string pairs,
 the plurality of second memory string pairs are configured to store a plurality of second store bits, respectively,   the plurality of second memory string pairs are configured to compare the plurality of second store bits and the plurality of input bits, to generate a second bit line signal of the plurality of bit line signals.   
     
     
         20 . The memory system of  claim 18 , wherein a quantity of the plurality of first memory string pairs is an half of a quantity of the plurality of memory blocks.