Pipelined Floating-Point Adder with Support for Forwarding Un-Normalized Mantissa Results for Dependent Instructions

Abstract

Techniques are disclosed relating to floating-point add pipelines. In some embodiments, floating-point add pipeline circuitry configured to perform a first add operation followed by a second add operation, where the second add operation specifies a first input operand that corresponds to a result of the first add operation. Adder circuitry may add mantissa values to generate a mantissa result. Forward circuitry may forward an un-normalized mantissa result from the adder circuitry as an input operand for the second add operation and exponent information from the first add operation. Left-shift circuitry may, prior to the adder circuitry in the pipeline, left-shift the un-normalized mantissa result based on the exponent information. The adder circuitry may add the shifted mantissa result for the second add operation. Disclosed techniques may allow execution of dependent add instructions, in a two-stage pipeline, without bubbles.

1 . An apparatus, comprising:
 floating-point add pipeline circuitry configured to perform a first add operation followed by a second add operation, wherein the second add operation specifies a first input operand that corresponds to a result of the first add operation, comprising:
 adder circuitry configured to add mantissa values to generate a mantissa result; 
 forward circuitry configured to forward:
 an un-normalized mantissa result from the adder circuitry as an input operand for the second add operation; and 
 exponent information from the first add operation; and 
 
 left-shift circuitry, prior to the adder circuitry in the pipeline, configured to left-shift the un-normalized mantissa result based on the exponent information, wherein the adder circuitry is configured to add the shifted mantissa result for the second add operation. 
   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 right-shift circuitry configured to right shift a second input operand of the second add operation;   wherein the right shift and the left shift are performed at least partially in parallel in the same clock cycle.   
     
     
         3 . The apparatus of  claim 1 , wherein the un-normalized forwarded mantissa value is generated by overflow control circuitry configured to shift the mantissa result from the adder circuitry based on an overflow signal. 
     
     
         4 . The apparatus of  claim 1 , further comprising:
 leading zero error control circuitry configured to:
 determine that a forwarded result has been selected as an anchor term for the second add operation; 
 detect that a leading zero anticipator result for the second add operation is less than a correct value; and 
 in response to the determination and detection, perform one or more shift operations to correct the leading zero anticipator result. 
   
     
     
         5 . The apparatus of  claim 1 , wherein the forwarded exponent information is an exponent selected as an anchor. 
     
     
         6 . The apparatus of  claim 1 , further comprising control circuitry configured to:
 determine whether a given add operation utilizes a forwarded un-normalized mantissa result; and   control the left-shift circuitry to:
 for a non-forwarding add operation, control the left-shift circuitry to normalize a mantissa result from the adder circuitry; and 
 for an add operation that utilizes a forwarded un-normalized mantissa result, control the left-shift circuitry to left-shift the un-normalized forwarded mantissa result. 
   
     
     
         7 . The apparatus of  claim 1 , further comprising:
 exponent control circuitry configured to control the left-shift circuitry based on:
 the forwarded exponent information; 
 an exponent of a second input operand of the second add operation; 
 a leading zero anticipator result; and 
 an overflow result. 
   
     
     
         8 . The apparatus of  claim 1 , further comprising:
 sign forward circuitry configured to forward an intermediate sign result of the first add operation.   
     
     
         9 . The apparatus of  claim 1 , wherein the floating-point add pipeline circuitry is configured to perform the second add operation immediately following the first add operation without any pipeline bubbles. 
     
     
         10 . The apparatus of  claim 1 , wherein the floating-point add pipeline circuitry:
 implements an N-stage pipeline;   is configured to perform the second add operation immediately following the first add operation; and   utilizes at most N-2 pipeline bubbles between the first and second add operations.   
     
     
         11 . The apparatus of  claim 1 , wherein the apparatus is a computing device that further includes:
 a display; and   network interface circuitry.   
     
     
         12 . A method, comprising:
 performing, by floating-point add pipeline circuitry of a computing system, a first add operation followed by a second add operation, wherein the second add operation specifies a first input operand that corresponds to a result of the first add operation, wherein the performing includes:
 adding mantissa values for the first add operation to generate an un-normalized intermediate mantissa result; 
 forwarding the un-normalized mantissa result as an input for the second add operation; 
 left-shifting the un-normalized forwarded mantissa result, based on forwarded exponent information from the first add operation; and 
 adding mantissa values for the second add operation, including the left-shifted mantissa result and a second mantissa value corresponding to a second input operand specified by the second add operation. 
   
     
     
         13 . The method of  claim 12 , wherein the un-normalized mantissa result is corrected prior to the forwarding based on an overflow signal. 
     
     
         14 . The method of  claim 12 , wherein the performing further includes
 determining that a forwarded result has been selected as an anchor term for the second add operation;   detecting that a leading zero anticipator result for the second add operation is less than a correct value; and   in response to the determining and detecting, performing one or more shift operations to correct the leading zero anticipator result.   
     
     
         15 . The method of  claim 12 , further comprising:
 using left-shift circuitry to perform the left-shifting; and   using the left-shift circuitry to left-shift a mantissa result for a third add operation that does not use any forwarded input operand.   
     
     
         16 . The method of  claim 12 , further comprising:
 determining a left-shift amount for the left-shifting based on:
 the forwarded exponent information; 
 an exponent of a second input operand; 
 a leading zero anticipator result; and 
 an overflow result. 
   
     
     
         17 . The method of  claim 12 , wherein the performing performs the second add operation immediately following the first add operation without any pipeline bubbles. 
     
     
         18 . A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:
 floating-point add pipeline circuitry configured to perform a first add operation followed by a second add operation, wherein the second add operation specifies a first input operand that corresponds to a result of the first add operation, comprising:
 adder circuitry configured to add mantissa values to generate a mantissa result; 
 forward circuitry configured to provide:
 an un-normalized mantissa result from the adder circuitry as an input operand for the second add operation; and 
 exponent information from the first add operation; and 
 
 left-shift circuitry, prior to the adder circuitry in the pipeline, configured to left-shift the un-normalized mantissa result based on the exponent information, wherein the adder circuitry is configured to add the shifted mantissa result for the second add operation. 
   
     
     
         19 . The non-transitory computer-readable medium of  claim 18 , further comprising:
 right-shift circuitry configured to right-shift a second input operand of the second add operation;   wherein the right-shift and the left shift are performed at least partially in parallel.   
     
     
         20 . The non-transitory computer-readable medium of  claim 18 , wherein the circuit further includes:
 leading zero error control circuitry configured to:
 determine that a forwarded result has been selected as an anchor term for the second add operation; 
 detect that a leading zero anticipator result for the second add operation is less than a correct value; and 
 in response to the determination and detection, perform one or more shift operations to correct the leading zero anticipator result.