Trench mosfet with reduced gate capacitances

Abstract

A trench MOSFET with reduced gate capacitances, and a method of making the same. The reduction of the gate capacitances is achieved with asymmetric dielectric gate oxide on the sidewalls and bottom of the trench, with the gate oxide being thinner on the channel side and thicker on the opposite side and bottom. Silicon is implanted into a partial MOSFET structure, resulting in silicon-rich silicon carbide. A trench is asymmetrically etched into the implanted silicon, leaving a thicker layer of the implanted silicon on the second sidewall and bottom of the trench than on the first sidewall. A layer of silicon dioxide is grown over the first and second sidewalls and bottom of the trench, and the growing oxide converts the silicon-rich silicon carbide into additional silicon dioxide, resulting in a thicker layer of silicon dioxide at the second sidewall and bottom of the trench than at the first sidewall.

1 . A trench metal oxide semiconductor field-effect transistor with a reduced gate capacitance, the trench metal oxide semiconductor field-effect transistor comprising:
 a volume of semiconductor material;   a channel through the volume of semiconductor material, the channel including a first end and a second end;   a source located at the first end of the channel;   a drain located at the second end of the channel;   a body;   a trench extending into the volume of semiconductor material alongside the channel, the trench including a first sidewall which is nearer to the channel, a second sidewall which is farther from the channel, and a bottom;   a gate located within the trench; and   a dielectric material between the gate and the trench, wherein a first average thickness of the dielectric material along the second sidewall and the bottom of the trench is thicker than a second average thickness of the dielectric material along the first sidewall of the trench.   
     
     
         2 . The trench metal oxide semiconductor field-effect transistor of  claim 1 , wherein the dielectric material results in a reduced gate capacitance relative to an otherwise identical transistor having the semiconductor material in place of the dielectric material, the reduced gate capacitance including a gate-source capacitance and a drain-source capacitance. 
     
     
         3 . The trench metal oxide semiconductor field-effect transistor of  claim 1 , wherein
 the semiconductor material is an N-type epitaxial semiconductor material;   the source includes an N+ material implanted into the N-type epitaxial semiconductor material;   the drain includes an N+ material substrate; and   the body includes a P+ material.   
     
     
         4 . The trench metal oxide semiconductor field-effect transistor of  claim 1 , wherein the dielectric material is silicon dioxide. 
     
     
         5 . The trench metal oxide semiconductor field-effect transistor of  claim 1 , wherein the first average thickness of the dielectric material along the second sidewall and bottom dielectric is between one-and-one-half (1.5) to two (2) times thicker than the second average thickness of the dielectric material along the first sidewall of the trench. 
     
     
         6 . The trench metal oxide semiconductor field-effect transistor of  claim 1 , further including a first electrical terminal coupled with the source, a second electrical terminal coupled with the drain, a third electrical terminal coupled with the gate, and a fourth electrical terminal coupled with the body. 
     
     
         7 . A method of making a trench metal oxide semiconductor field-effect transistor with a reduced gate capacitance, beginning with a volume of semiconductor material, a channel through the volume of semiconductor material, the channel including a first end and a second end, a source located at the first end of the channel, a drain located at the second end of the channel, and a body, the method comprising:
 implanting a volume of silicon into the semiconductor material, resulting in a silicon-rich semiconductor material that extends alongside the channel;   etching a trench asymmetrically into the silicon-rich semiconductor material, the trench including a first sidewall which is nearer to the channel, a second sidewall which is farther from the channel, and a bottom, wherein the trench is asymmetrical in that a first average thickness of the silicon-rich semiconductor material remaining along the second sidewall and the bottom of the trench is thicker than a second average thickness of the silicon-rich semiconductor material remaining along the first sidewall;   depositing a dielectric material at the first sidewall, the second sidewall, and the bottom of the trench, wherein the dielectric material converts the silicon-rich semiconductor material into additional dielectric material, and wherein a first total average thickness of the dielectric material along the second sidewall and the bottom of the trench is thicker than a second total average thickness of the dielectric material along the first sidewall; and   depositing a polysilicon material in the trench to form a gate.   
     
     
         8 . The method of  claim 7 , wherein the dielectric material results in a reduced gate capacitance relative to an otherwise identical transistor having the semiconductor material in place of the dielectric material, the reduced gate capacitance including a gate-source capacitance and a drain-source capacitance. 
     
     
         9 . The method of  claim 7 , wherein
 the semiconductor material is an N-type epitaxial semiconductor material;   the source includes an N+ material implanted into the N-type epitaxial semiconductor material;   the drain includes an N+ material substrate; and   the body includes a P+ material.   
     
     
         10 . The method of  claim 7 , wherein the semiconductor material is silicon carbide, the dielectric material is silicon dioxide, and the silicon dioxide converts the silicon-rich semiconductor material into additional silicon dioxide. 
     
     
         11 . The method of  claim 7 , wherein the first total average thickness of dielectric material along the second sidewall and bottom of the trench is between one-and-one-half (1.5) to two (2) times thicker than the second total average thickness along the first sidewall of the trench. 
     
     
         12 . The method of  claim 7 , further including adding a first electrical terminal to the source, adding a second electrical terminal to the drain, adding a third electrical terminal to the gate, and adding a fourth electrical terminal to the body. 
     
     
         13 . A method of making a trench metal oxide semiconductor field-effect transistor with a reduced gate capacitance, beginning with a volume of N-type epitaxial silicon carbide semiconductor material, a channel through the volume of N-type epitaxial semiconductor material, the channel including a first end and a second end, a source including an N+ material located at the first end of the channel, a drain including an N+ material substrate located at the second end of the channel, and a body including a P+ material, the method comprising:
 implanting a volume of silicon into the N-type epitaxial semiconductor material, resulting in a silicon-rich silicon carbide semiconductor material that extends alongside the channel;   etching a trench asymmetrically into the silicon-rich silicon carbide semiconductor material, the trench including a first sidewall which is nearer to the channel, a second sidewall which is farther from the body, and a bottom, wherein the trench is asymmetrical in that a first average thickness of the silicon-rich silicon carbide semiconductor material remaining along the second sidewall and the bottom of the trench is thicker than a second average thickness of the silicon-rich silicon carbide semiconductor material remaining along the first sidewall;   depositing a silicon dioxide dielectric material at the first sidewall, the second sidewall, and the bottom of the trench, wherein the silicon dioxide dielectric material converts the silicon-rich silicon carbide semiconductor material into additional silicon dioxide dielectric material, and wherein a first total average thickness of the silicon dioxide dielectric material along the second sidewall and the bottom of the trench is thicker than a second total average thickness of the silicon dioxide dielectric material along the first sidewall; and   depositing a polysilicon material in the trench to form a gate.   
     
     
         14 . The method of  claim 13 , wherein the dielectric material results in a reduced gate capacitance relative to an otherwise identical transistor having the semiconductor material in place of the dielectric material, the reduced gate capacitance including a gate-source capacitance and a drain-source capacitance. 
     
     
         15 . The method of  claim 13 , wherein the first total average thickness of dielectric material along the second sidewall and bottom of the trench is between one-and-one-half (1.5) to two (2) times thicker than the second total average thickness along the first sidewall of the trench. 
     
     
         16 . The method of  claim 13 , further adding a first electrical terminal to the source, adding a second electrical terminal to the drain, adding a third electrical terminal to the gate, and adding a fourth electrical terminal to the body.