Techniques for matte white metallic finish of electronic devices
Abstract
An enclosure for an electronic device includes an aluminum alloy substrate and an anodic oxide coating disposed on the aluminum alloy substrate, the anodic oxide coating having a nano-scale etched pattern. The enclosure includes a matte-white finish having a flop index between about 2 and about 10. The anodic oxide coating has a L* value of greater than about 90, an a* value of less than about 1, and a b* value of less than about 2. The enclosure includes a sealant disposed on the anodic oxide coating, the sealant including a sol-gel coating, a hard-coat, an anodic electrophoretic deposition coating, or a combination thereof.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An enclosure for an electronic device, comprising:
an aluminum alloy substrate; and an anodic oxide coating disposed on the aluminum alloy substrate, the anodic oxide coating having a nano-scale etched pattern; wherein the enclosure comprises a matte-white finish having a flop index between about 2 and about 10.
2 . The enclosure of claim 1 , wherein the enclosure comprises a sealant disposed on the anodic oxide coating, the sealant comprising a sol-gel coating, a clear coat, an anodic electrophoretic deposition coating, or a combination thereof.
3 . The enclosure of claim 2 , wherein the sealant comprises a thickness less than about 5 microns.
4 . The enclosure of claim 2 , wherein the anodic layer comprises a thickness between about 10 microns and about 20 microns.
5 . The enclosure of claim 2 , wherein a thickness of the sealant is proportional to a gloss value of the enclosure.
6 . The enclosure of claim 1 , wherein the anodic oxide coating has a L* value of greater than about 90, an a* value of less than about 1, and a b* value of less than about 2.
7 . The enclosure of claim 1 , wherein the anodic oxide coating has a 60-degree gloss measurement less than 30 gloss units.
8 . The enclosure of claim 1 , wherein the enclosure comprises a surface hardness of about 300 HV 0.05 or greater.
9 . A housing, comprising:
an aluminum substrate; and an anodic layer disposed on at least a portion of the substrate and configured to diffuse ambient light, wherein the housing comprises a matte-white finish having a L* value greater than about 90.
10 . The enclosure of claim 9 , wherein the anodic layer comprises an etched pattern having fissures configured to diffuse the ambient light.
11 . The enclosure of claim 9 , wherein the housing comprises a sealant disposed on the anodic layer, wherein the sealant comprises a sol-gel coating, a hard-coat, an anodic electrophoretic deposition layer, or a combination thereof.
12 . The enclosure of claim 11 , wherein the sealant comprises a thickness less than about 5 microns and the anodic layer comprises a thickness between about 10 microns and about 20 microns.
13 . The enclosure of claim 9 , wherein the anodic layer exhibits a L* value of greater than about 90, an a* value of less than about 1, and a b* value of less than about 2.
14 . The enclosure of claim 9 , wherein the anodic layer exhibits a 60-degree gloss measurement between about 5 and about 10 gloss units.
15 . A method for forming a surface on a substrate having a flop index between about 2 and about 10, comprising:
forming an aluminum alloy substrate; anodizing a porous oxide layer on the aluminum alloy substrate; etching the porous oxide layer to form a nano-scale etched pattern; and sealing the porous oxide layer.
16 . The method of claim 15 , wherein etching the porous oxide layer comprises etching the porous oxide layer in aluminum sulfate at between about 30 and 80° C.
17 . The method of claim 15 , wherein anodizing the porous oxide layer comprises:
immersing the aluminum alloy substrate in an electrolyte comprising between about 150 and 250 g/L of sulfuric acid; and applying a current having a current density between about 0.5 A/dm 2 and 2.5 A/dm 2 at about 20° C.
18 . The method of claim 15 , wherein a flop index value of the surface is inversely proportional to a duration of time etching the porous oxide layer.
19 . The method of claim 15 , wherein sealing the porous oxide layer comprises:
performing an anodic electrophoretic deposition on the etched porous oxide layer or applying a sol-gel coating or a hard-coat to the etched porous oxide layer.
20 . The method of claim 15 , wherein the sealed porous oxide layer exhibits a L* value of greater than about 90, an a* value of less than about 1, and a b* value of less than about 2.Join the waitlist — get patent alerts
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