Semiconductor device and methods of formation

Abstract

A transistor structure (e.g., a backend transistor structure in an interconnect layer of a semiconductor device) is formed to include an oxide-semiconductor channel layer having a high electron concentration oxide-semiconductor material. The high electron concentration oxide-semiconductor material enables a low threshold voltage and a low channel resistance to be achieved for the oxide-semiconductor channel layer, which enables a high on current to be achieved for the transistor structure. To provide channel control over the oxide-semiconductor channel layer, an oxide-semiconductor barrier layer is included between the source/drain electrodes of the transistor structure and the oxide-semiconductor channel layer. The oxide-semiconductor barrier layer includes a low electron concentration oxide-semiconductor material, which enables increased control over the conductivity of the oxide-semiconductor channel layer to be achieved, which enables a low off current leakage to be achieved for the transistor structure.

What is claimed is: 
     
         1 . A transistor structure, comprising:
 a gate electrode;   an oxide-semiconductor channel layer;   a gate dielectric layer vertically between the gate electrode and the oxide-semiconductor channel layer;   a source/drain electrode coupled to the oxide-semiconductor channel layer; and   an oxide-semiconductor barrier layer between the oxide-semiconductor channel layer and the source/drain electrode,
 wherein an electron concentration in the oxide-semiconductor barrier layer is less than an electron concentration in the oxide-semiconductor channel layer. 
   
     
     
         2 . The transistor structure of  claim 1 , wherein the oxide-semiconductor barrier layer is in direct physical contact with the source/drain electrode and is in direct physical contact with the oxide-semiconductor channel layer. 
     
     
         3 . The transistor structure of  claim 1 , wherein the oxide-semiconductor barrier layer is a first oxide-semiconductor barrier layer in the transistor structure; and
 wherein the transistor structure further comprises:
 a second oxide-semiconductor barrier layer between the first oxide-semiconductor barrier layer and the source/drain electrode,
 wherein an electron concentration in the second oxide-semiconductor barrier layer is greater than the electron concentration in the first oxide-semiconductor barrier layer. 
 
   
     
     
         4 . The transistor structure of  claim 3 , wherein the second oxide-semiconductor barrier layer is located between sidewalls of the source/drain electrode and the first oxide-semiconductor barrier layer; and
 wherein the second oxide-semiconductor barrier layer is located between a bottom surface of the source/drain electrode and the first oxide-semiconductor barrier layer.   
     
     
         5 . The transistor structure of  claim 1 , wherein a thickness of the oxide-semiconductor barrier layer is greater than approximately 0 nanometers and less than approximately 10 nanometers. 
     
     
         6 . The transistor structure of  claim 1 , wherein the oxide-semiconductor channel layer is vertically between the gate electrode and the oxide-semiconductor barrier layer. 
     
     
         7 . The transistor structure of  claim 1 , wherein the oxide-semiconductor barrier layer is laterally between the gate electrode and the source/drain electrode. 
     
     
         8 . The transistor structure of  claim 1 , wherein the electron concentration in the oxide-semiconductor barrier layer is included in a range of approximately 5×10 16  electrons per cubic centimeter to approximately 1×10 18  electrons per cubic centimeter; and
 wherein the electron concentration in the oxide-semiconductor channel layer is included in a range of greater than approximately 1×10 18  electrons per cubic centimeter and less than or approximately equal to 1×10 20  electrons per cubic centimeter. 
 
     
     
         9 . A transistor structure, comprising:
 a gate electrode;   an oxide-semiconductor channel layer;   a gate dielectric layer vertically between the gate electrode and the oxide-semiconductor channel layer;   a source/drain electrode coupled to the oxide-semiconductor channel layer; and   an oxide-semiconductor barrier layer between the oxide-semiconductor channel layer and the source/drain electrode,
 wherein a hydrogen concentration in the oxide-semiconductor channel layer is greater than a hydrogen concentration in the oxide-semiconductor barrier layer. 
   
     
     
         10 . The transistor structure of  claim 9 , wherein an oxygen concentration in the oxide-semiconductor barrier layer is greater than an oxygen concentration in the oxide-semiconductor channel layer. 
     
     
         11 . The transistor structure of  claim 9 , wherein a fluorine concentration in the oxide-semiconductor barrier layer is greater than a fluorine concentration in the oxide-semiconductor channel layer. 
     
     
         12 . The transistor structure of  claim 9 , wherein the oxide-semiconductor barrier layer is in direct physical contact with the source/drain electrode and is in direct physical contact with the oxide-semiconductor channel layer. 
     
     
         13 . The transistor structure of  claim 9 , wherein the oxide-semiconductor barrier layer is a first oxide-semiconductor barrier layer in the transistor structure; and
 wherein the transistor structure further comprises:
 a second oxide-semiconductor barrier layer between the first oxide-semiconductor barrier layer and the source/drain electrode,
 wherein a hydrogen concentration in the second oxide-semiconductor barrier layer is greater than the hydrogen concentration in the first oxide-semiconductor barrier layer. 
 
   
     
     
         14 . The transistor structure of  claim 9 , wherein a portion of the oxide-semiconductor barrier layer at a bottom of the source/drain electrode is recessed in the oxide-semiconductor channel layer. 
     
     
         15 . A method, comprising:
 forming an oxide-semiconductor channel layer of a backend transistor structure;   forming a backend dielectric layer above the oxide-semiconductor channel layer;   forming a recess in the backend dielectric layer such that the oxide-semiconductor channel layer is exposed through the recess;   forming an oxide-semiconductor barrier layer in the recess,
 wherein an oxygen concentration in the oxide-semiconductor barrier layer is greater than an oxygen concentration in the oxide-semiconductor channel layer; and 
   forming a source/drain electrode above the oxide-semiconductor barrier layer in the recess.   
     
     
         16 . The method of  claim 15 , wherein the recess extends into a portion of the oxide-semiconductor channel layer; and
 wherein forming the oxide-semiconductor barrier layer comprises:
 forming the oxide-semiconductor barrier layer such that a portion of the oxide-semiconductor barrier layer, at a bottom of the recess, is included on the oxide-semiconductor channel layer. 
   
     
     
         17 . The method of  claim 15 , wherein forming the oxide-semiconductor barrier layer comprises:
 conformally depositing the oxide-semiconductor barrier layer on sidewalls of the recess and on a bottom surface of the recess.   
     
     
         18 . The method of  claim 15 , wherein forming the oxide-semiconductor barrier layer comprises:
 forming a first oxide-semiconductor barrier layer in the recess; and   wherein the method further comprises:
 forming a second oxide-semiconductor barrier layer on the first oxide-semiconductor barrier layer in the recess,
 wherein an oxygen concentration in the second oxide-semiconductor barrier layer is less than the oxygen concentration in the first oxide-semiconductor barrier layer. 
 
   
     
     
         19 . The method of  claim 18 , wherein forming the source/drain electrode comprises:
 forming the source/drain electrode on the second oxide-semiconductor barrier layer in the recess.   
     
     
         20 . The method of  claim 15 , wherein forming the source/drain electrode comprises:
 forming the source/drain electrode directly on the oxide-semiconductor barrier layer in the recess.