US2026047145A1PendingUtilityA1
Stacked multi-channel structure and method for manufacturing same, and thin film transistor comprising same
Est. expiryApr 18, 2043(~16.7 yrs left)· nominal 20-yr term from priority
H10D 30/6757H10D 30/6755H10D 30/031H10D 99/00H10D 30/6739
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Claims
Abstract
A thin film transistor is provided. The thin film transistor may comprise a stacked channel structure in which a first material layer including an oxide semiconductor and a second material layer including a metal oxide insulator are stacked, wherein the channel structure forms a multi-channel by stacking a plurality of stacks each having the first material layer and the second material layer stacked, and as the number of the stacks stacked increases, mobility and subthreshold swing may increase.
Claims
exact text as granted — not AI-modified1 . A thin film transistor including a channel structure in which a first material layer including an oxide semiconductor and a second material layer including a metal oxide insulator are stacked,
wherein the channel structure forms a multi-channel by stacking a plurality of stacks, in which the first material layer and the second material layer are stacked in each of the stacks, and mobility and subthreshold swing increase as a stacking number of the stacks increases.
2 . The thin film transistor of claim 1 , wherein an increase rate of the mobility according to the increase in the stacking number of the stacks is higher than an increase rate of the subthreshold swing.
3 . The thin film transistor of claim 1 , wherein a variation in a threshold voltage is maintained at 10% or less even when the stacking number of the stacks increases.
4 . The thin film transistor of claim 3 , wherein the threshold voltage is maintained in a range of 0.09 V to 0.19 V even when the stacking number of the stacks increases.
5 . The thin film transistor of claim 1 , wherein the stacking number of the stacks is greater than equal to 5, and less than or equal to 10.
6 . The thin film transistor of claim 1 , wherein a thickness of the second material layer is less than 4 nm.
7 . The thin film transistor of claim 1 , wherein the oxide semiconductor includes indium gallium zinc oxide (IGZO).
8 . The thin film transistor of claim 1 , wherein the metal oxide insulator includes aluminum oxide (Al 2 O 3 ).
9 . The thin film transistor of claim 1 , wherein an amount of movement of carriers within the first material layer that is arranged relatively close to a gate is greater than an amount of movement of carriers within the first material layer that is arranged relatively far from the gate.
10 . A method for manufacturing a channel structure, the method comprising:
preparing a substrate; forming a first material layer including an oxide semiconductor on the substrate by a plasma-enhanced atomic layer deposition (PEALD) process; and forming a second material layer including a metal oxide insulator on the first material layer by a PEALD process, wherein the forming of the first material layer and the forming of the second material layer are alternately repeated so as to form a multi-channel.
11 . The method of claim 10 , wherein the forming of the first material layer includes:
reacting an indium (In) precursor, a gallium (Ga) precursor, a zinc (Zn) precursor, and oxygen plasma (O 2 plasma) on the substrate, and the forming of the second material layer includes: reacting an aluminum (Al) precursor and oxygen plasma (O 2 plasma) on the first material layer.
12 . The method of claim 10 , wherein the first material layer and the second material layer are formed by an in-situ process.Join the waitlist — get patent alerts
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