Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same

Abstract

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

What is claimed: 
     
         1 .- 20 . (canceled) 
     
     
         21 . A method comprising:
 forming a semiconductor heterostructure over a substrate;   forming a superconducting layer over the semiconductor heterostructure;   forming a first gate, having a first top surface, adjacent to a first side of the semiconductor heterostructure; and   forming a second gate, having a second top surface, adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, wherein each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a top surface of the semiconductor heterostructure by a predetermined offset amount, wherein the predetermined offset amount is selected to ensure that a horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure to reduce an effect of any line edge roughness (LER) associated with the superconducting layer.   
     
     
         22 . The method of  claim 21 , wherein the horizontally-confined electrostatic channel comprises one of a 2-dimensional electron gas (2-DEG) channel or a 2-dimensional hole gas (2-DHG) channel. 
     
     
         23 . The method of  claim 21 , wherein the semiconductor-superconductor hybrid device is operable as a nanowire having a tunable width. 
     
     
         24 . The method of  claim 21 , further comprising determining the predetermined offset by testing samples of multiple devices to increase a mobility of electrons within the horizontally-confined electrostatic channel. 
     
     
         25 . The method of  claim 21 , further comprising determining the predetermined offset by testing samples of multiple devices to increase a density of electrons within the horizontally-confined electrostatic channel. 
     
     
         26 . The method of  claim 21 , wherein each of the first semiconductor heterostructure and the second semiconductor heterostructure comprises a first layer of indium arsenide or aluminum arsenide, a second layer of indium arsenide, and a third layer of indium arsenide or gallium arsenide. 
     
     
         27 . A method comprising:
 forming a semiconductor heterostructure over a substrate;   forming a superconducting layer over the semiconductor heterostructure;   forming a first gate, having a first top surface, adjacent to a first side of the semiconductor heterostructure;   forming a second gate, having a second top surface, adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, wherein each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a top surface of the semiconductor heterostructure by a predetermined offset amount, wherein the predetermined offset amount is selected to ensure that a horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure to reduce an effect of any line edge roughness (LER) associated with the superconducting layer; and   forming a first terminal coupled to the first gate and a second terminal coupled to the second gate, wherein the electric field is generated by an application of a first voltage to the first terminal and a second voltage to the second terminal.   
     
     
         28 . The method of  claim 27 , wherein an amount of the first voltage and an amount of the second voltage is selected to tune a width associated with the horizontally-confined electrostatic channel. 
     
     
         29 . The method of  claim 27 , wherein the horizontally-confined electrostatic channel comprises one of a 2-dimensional electron gas (2-DEG) channel or a 2-dimensional hole gas (2-DHG) channel. 
     
     
         30 . The method of  claim 27 , further comprising forming a first terminal coupled to the first gate and a second terminal coupled to the second gate, wherein the electric field is generated by an application of a first voltage to the first terminal and a second voltage to the second terminal. 
     
     
         31 . The method of  claim 29 , wherein each of the first semiconductor heterostructure and the second semiconductor heterostructure comprises a first layer of indium arsenide or aluminum arsenide, a second layer of indium arsenide, and a third layer of indium arsenide or gallium arsenide. 
     
     
         32 . The method of  claim 27 , wherein the semiconductor-superconductor hybrid device is operable as a nanowire having a tunable width. 
     
     
         33 . The method of  claim 27 , further comprising determining the predetermined offset by testing samples of multiple devices to increase a mobility of electrons within the horizontally-confined electrostatic channel. 
     
     
         34 . The method of  claim 27 , further comprising determining the predetermined offset by testing samples of multiple devices to increase a density of electrons within the horizontally-confined electrostatic channel. 
     
     
         35 . A method comprising:
 forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure formed over a substrate;   forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure;   forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, wherein a top surface of each of the left gate and the right gate is offset vertically from a top surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount, wherein the semiconductor-superconductor hybrid device is configured to form a horizontally-confined electrostatic channel in a respective isolated semiconductor heterostructure in response to an application of an electric field to the respective isolated semiconductor heterostructure via a respective left gate and a respective right gate, wherein the predetermined offset amount is selected to ensure that the horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the respective isolated semiconductor heterostructure to reduce an effect of any structural disorder associated with an interface of the superconducting layer with the respective isolated semiconductor heterostructure, and wherein the structural disorder associated with the interface comprises line edge roughness (LER) associated with the superconducting layer; and   forming a superconducting layer formed over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.   
     
     
         36 . The method of  claim 35 , wherein the horizontally-confined electrostatic channel comprises one of a 2-dimensional electron gas (2-DEG) channel or a 2-dimensional hole gas (2-DHG) channel. 
     
     
         37 . The method of  claim 35 , wherein the semiconductor-superconductor hybrid device is operable as a nanowire having a tunable width. 
     
     
         38 . The method of  claim 35 , further comprising determining the predetermined offset by testing samples of multiple devices to increase a mobility of electrons within the horizontally-confined electrostatic channel. 
     
     
         39 . The method of  claim 35 , further comprising determining the predetermined offset by testing samples of multiple devices to increase a density of electrons within the horizontally-confined electrostatic channel. 
     
     
         40 . The method of  claim 35 , wherein each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure comprises a first layer of indium arsenide or aluminum arsenide, a second layer of indium arsenide, and a third layer of indium arsenide or gallium arsenide.