Semiconductor device performing tests and test method of the semiconductor device

Abstract

A semiconductor device includes a test control circuit generating an external output test pattern based on a test enable signal, an internal output test pattern and an output command signal based on an external input test pattern, and a check result signal based on input read data, an external input/output (IO) circuit generating the external input test pattern by performing a loopback operation based on the external output test pattern, an internal IO circuit generating an internal input test pattern based on the internal output test pattern and an input command signal based on the output command signal and outputting the input read data based on output read data, and a storage circuit storing the internal input test pattern based on the internal input test pattern and the input command signal and extracting the output read data based on the internal input test pattern and the input command signal.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a test control circuit configured to generate an external output test pattern based on a test enable signal, configured to generate an internal output test pattern and an output command signal based on an external input test pattern, and configured to generate a check result signal based on input read data;   an external input and output (IO) circuit configured to generate the external input test pattern by performing a loopback operation based on the external output test pattern;   an internal IO circuit configured to generate an internal input test pattern based on the internal output test pattern, configured to generate an input command signal based on the output command signal, and configured to output the input read data based on output read data; and   a storage circuit configured to store the internal input test pattern based on the internal input test pattern and the input command signal and configured to extract the output read data based on the internal input test pattern and the input command signal.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the test control circuit comprises:
 a test pattern generation circuit configured to generate the external output test pattern based on the test enable signal;   a memory controller configured to generate the internal output test pattern and the output command signal based on the external input test pattern; and   a check circuit configured to generate the check result signal based on whether the external input test pattern and the input read data are identical with each other.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the test control circuit sequentially generates the external output test pattern having a first pattern for a write operation and the external output test pattern having a second pattern for a read operation. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the external IO circuit comprises:
 an IO control circuit configured to generate a middle output test pattern based on the external output test pattern and configured to generate the external input test pattern based on a middle input test pattern;   a transmitter configured to generate a feedback test pattern based on the middle output test pattern; and   a receiver configured to generate the middle input test pattern based on the feedback test pattern.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the loopback operation is an operation of receiving the external output test pattern output from the external IO circuit being received again through a reception path within the external IO circuit. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the internal IO circuit comprises:
 an interface circuit configured to generate an internal forward test pattern based on the internal output test pattern, configured to generate a forward command signal based on the output command signal, and configured to generate the input read data based on forward read data; and   a through silicon via (TSV) circuit configured to output the internal input test pattern based on the internal forward test pattern, configured to output the input command signal based on the forward command signal, and configured to output the forward read data based on the output read data.   
     
     
         7 . A memory system comprising:
 a plurality of die cores stacked over a base die,   the base die comprises:   a test control circuit configured to generate an external output test pattern based on a test enable signal, configured to generate an internal output test pattern and an output command signal based on an external input test pattern, and configured to generate a check result signal based on input read data;   an external input and output (IO) circuit configured to generate the external input test pattern by performing a loopback operation based on the external output test pattern; and   an internal IO circuit configured to generate an internal input test pattern based on the internal output test pattern, configured to generate an input command signal based on the output command signal, and configured to output the input read data based on output read data,   wherein each of the plurality of die cores stores the internal input test pattern based on the internal input test pattern and the input command signal and outputs the output read data based on the internal input test pattern and the input command signal.   
     
     
         8 . The memory system of  claim 7 , wherein the test control circuit comprises:
 a test pattern generation circuit configured to generate the external output test pattern based on the test enable signal;   a memory controller configured to generate the internal output test pattern and the output command signal based on the external input test pattern; and   a check circuit configured to generate the check result signal based on whether the external input test pattern and the input read data are identical with each other.   
     
     
         9 . The memory system of  claim 8 , wherein the test control circuit sequentially generates the external output test pattern having a first pattern for a write operation and the external output test pattern having a second pattern for a read operation. 
     
     
         10 . The memory system of  claim 7 , wherein the external IO circuit comprises:
 an IO control circuit configured to generate a middle output test pattern based on the external output test pattern and configured to generate the external input test pattern based on a middle input test pattern;   a transmitter configured to generate a feedback test pattern based on the middle output test pattern; and   a receiver configured to generate the middle input test pattern based on the feedback test pattern.   
     
     
         11 . The memory system of  claim 7 , wherein the loopback operation is an operation of receiving the external output test pattern output from the external IO circuit being received again through a reception path within the external IO circuit. 
     
     
         12 . The memory system of  claim 7 , wherein the internal IO circuit comprises:
 an interface circuit configured to generate an internal forward test pattern based on the internal output test pattern, configured to generate a forward command signal based on the output command signal, and configured to generate the input read data based on forward read data; and   a through silicon via (TSV) circuit configured to output the internal input test pattern based on the internal forward test pattern, configured to output the input command signal based on the forward command signal, and configured to output the forward read data based on the output read data.   
     
     
         13 . A semiconductor device comprises:
 a test control circuit configured to generate an internal output test pattern and an output command signal based on a test enable signal and configured to generate a check result signal based on input read data;   an internal input and output (IO) circuit configured to generate an internal input test pattern based on the internal output test pattern, configured to generate an input command signal based on the output command signal, and configured to output the input read data based on output read data; and   a storage circuit configured to store the internal input test pattern based on the internal input test pattern and the input command signal and configured to output the output read data based on the internal input test pattern and the input command signal.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the test control circuit comprises:
 a test pattern generation circuit configured to generate a middle test pattern based on the test enable signal;   a memory controller configured to generate the internal output test pattern and the output command signal based on the middle test pattern; and   a check circuit configured to generate the check result signal based on whether the middle test pattern and the input read data are identical with each other.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the test control circuit sequentially generates the middle test pattern having a first pattern for a write operation and the middle test pattern having a second pattern for a read operation. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the internal IO circuit comprises:
 an interface circuit configured to generate an internal forward test pattern based on the internal output test pattern, configured to generate a forward command signal based on the output command signal, and configured to generate the input read data based on forward read data; and   a through silicon via (TSV) circuit configured to output the internal input test pattern based on the internal forward test pattern, configured to output the input command signal based on the forward command signal, and configured to output the forward read data based on the output read data.   
     
     
         17 . A memory system comprising:
 a plurality of die cores stacked over a base die,   the base die comprises:   a test control circuit configured to generate an internal output test pattern and an output command signal based on a test enable signal and configured to generate a check result signal based on input read data; and   an internal input and output (IO) circuit configured to generate an internal input test pattern based on the internal output test pattern, configured to generate an input command signal based on the output command signal, and configured to output the input read data based on output read data,   wherein each of the plurality of die cores comprises a storage circuit configured to store the internal input test pattern based on the internal input test pattern and the input command signal and configured to output the output read data based on the internal input test pattern and the input command signal.   
     
     
         18 . The memory system of  claim 17 , wherein the test control circuit comprises:
 a test pattern generation circuit configured to generate a middle test pattern based on the test enable signal;   a memory controller configured to generate the internal output test pattern and the output command signal based on the middle test pattern; and   a check circuit configured to generate the check result signal based on whether the middle test pattern and the input read data are identical with each other.   
     
     
         19 . The memory system of  claim 18 , wherein the test control circuit sequentially generates the middle test pattern having a first pattern for a write operation and the middle test pattern having a second pattern for a read operation. 
     
     
         20 . The memory system of  claim 17 , wherein the internal IO circuit comprises:
 an interface circuit configured to generate an internal forward test pattern based on the internal output test pattern, configured to generate a forward command signal based on the output command signal, and configured to generate the input read data based on forward read data; and   a through silicon via (TSV) circuit configured to output the internal input test pattern based on the internal forward test pattern, configured to output the input command signal based on the forward command signal, and configured to output the forward read data based on the output read data.   
     
     
         21 . A method of checking when a data input and output (IO) path and a memory cell are poor, the method comprising:
 a first operation determination process of entering a test mode based on a test enable signal and determining whether a command signal corresponds to a write operation or a read operation;   a first write process of generating a test pattern for the write operation and performing a loopback operation when the command signal is determined to correspond to the write operation and storing a test pattern for the write operation in a storage circuit;   a first read process of generating a test pattern for the read operation and performing a loopback operation when the command signal is determined to correspond to the read operation and extracting read data from the storage circuit;   a first check process of performing a check operation of checking whether a data input and output (IO) path and a memory cell are poor by outputting a check result signal based on whether the test pattern for the write operation and the read data are identical with each other when the first read process is completed; and   a first termination determination process of re-entering the first operation determination process when the test enable signal is determined to have been activated and terminating the test mode when the test enable signal is determined to have been deactivated, when the first write process or the first read process is completed.   
     
     
         22 . The method of  claim 21 , wherein the first write process comprises:
 generating a first external output test pattern based on the test enable signal;   outputting the first external output test pattern as a first external input test pattern by performing the loopback operation based on the first external output test pattern;   generating a first internal output test pattern and a first output command signal based on the first external input test pattern;   generating a first internal input test pattern based on the first internal output test pattern and generating a first input command signal based on the first output command signal; and   storing the first internal input test pattern in a storage circuit based on the first internal input test pattern and the first input command signal.   
     
     
         23 . The method of  claim 21 , wherein the first read process comprises:
 generating a second external output test pattern based on the test enable signal;   outputting the second external output test pattern as a second external input test pattern by performing a loopback operation the second external output test pattern;   generating a second output command signal based on the second external input test pattern;   generating a second input command signal based on the second output command signal; and   extracting the read data from the storage circuit based on the second input command signal.   
     
     
         24 . The method of  claim 21 , wherein the first check process comprises:
 determining whether the first external output test pattern and the read data are identical with each other;   checking whether the data IO path and the memory cell are poor by activating the check result signal when the first external output test pattern and the read data are identical with each other; and   checking whether the data IO path and the memory cell are poor by deactivating the check result signal when the first external output test pattern and the read data are different from each other.   
     
     
         25 . A method of checking whether a data input and output (IO) path and a memory cell are poor, the method comprising:
 a second operation determination process of entering a test mode based on a test enable signal and determining whether a command signal corresponds to a write operation or a read operation;   a second write process of generating a test pattern for the write operation within a semiconductor device and storing write data in a storage circuit when the command signal is determined to correspond to the write operation;   a second read process of generating a test pattern for the read operation within the semiconductor device and extracting read data from the storage circuit when the command signal is determined to correspond to the read operation;   a second check process of performing a check operation of checking whether a data IO path and a memory cell are poor by outputting a check result signal based on whether the write data and the read data are identical with each other when the second read process is completed; and   a second termination determination process of re-entering the second operation determination process when the test enable signal is determined to have been activated and terminating the test mode when the test enable signal is determined to have been deactivated, when the second write process or the second read process is completed.   
     
     
         26 . The method of  claim 25 , wherein the second write process comprises:
 generating a first internal output test pattern and a first output command signal based on the test enable signal within the semiconductor device;   generating a first internal input test pattern based on the first internal output test pattern and generating a first input command signal based on the first output command signal; and   storing the first internal input test pattern in the storage circuit based on the first internal input test pattern and the first input command signal.   
     
     
         27 . The method of  claim 25 , wherein the second read process comprises:
 generating a second output command signal based on the test enable signal within the semiconductor device;   generating a second input command signal based on the second output command signal; and   extracting the read data from the storage circuit based on the second input command signal.   
     
     
         28 . The method of  claim 25 , wherein the second check process comprises:
 determining whether a first internal output test pattern and the read data are identical with each other;   checking whether the data IO path and the memory cell are poor by activating the check result signal when the first internal output test pattern and the read data are identical with each other; and   checking whether the data IO path and the memory cell are poor by deactivating the check result signal when the first internal output test pattern and the read data are different from each other.