Customized instruction-set cryptography engine

Abstract

A lattice-based cryptography engine includes an interface configured to receive a lattice-based cryptographic operation request including corresponding operands. A register map is configured to store the operands and response to the request. A controller is coupled to receive the operands and output a sequence of instructions responsive to the request. A plurality of hardware units is coupled to receive and execute the instructions to generate the response. Each instruction is designated for one of the plurality of hardware units. A memory is coupled to the hardware units.

1 . A computer implemented method comprising:
 receiving a request, including operands, from a requestor for a lattice-based cryptographic operation via an application programming interface of a hardware cryptographic engine;   storing the operands in a register map of the engine;   sequencing instructions corresponding to the request;   providing sequenced instructions to one or more cryptographic hardware units of the engine;   executing the sequenced instructions to generate output data responsive to the request;   storing the output data in the register map; and   transferring the output data from the register map to the requestor.   
     
     
         2 . The method of  claim 1  wherein sequencing instructions comprises:
 reading a set of instructions corresponding to the cryptographic operation from a read only memory (ROM); and 
 decoding the set of instructions. 
 
     
     
         3 . The method of  claim 2  wherein sequencing instructions further comprises tracking the instructions via a program counter. 
     
     
         4 . The method of  claim 2  wherein the ROM includes sets of instructions, each set corresponding to different cryptographic operations. 
     
     
         5 . The method of  claim 4  wherein the different cryptographic operations include key generation, signature generation, and signature verification. 
     
     
         6 . The method of  claim 1  wherein the instructions are executed by at least one of hardware sampler units, a hardware NTT unit, and hardware auxiliary units. 
     
     
         7 . The method of  claim 6  wherein the hardware sampler units include a rejection sampler unit, a rejection bounded sampler unit, and sample InBall unit. 
     
     
         8 . The method of  claim 6  wherein the hardware auxiliary units include a MakeHint unit, a UseHint unit, and a HintSum unit. 
     
     
         9 . The method of  claim 6  wherein the instructions are further executed by a hashing unit that includes a serial-in parallel-out (SIPO) memory, a Keccak unit, and a parallel-in serial-out (PISO) memory. 
     
     
         10 . A lattice-based cryptography engine comprising:
 an interface configured to receive a lattice-based cryptographic operation request including corresponding operands;   a register map configured to store the operands and response to the request;   a controller coupled to receive the operands and output a sequence of instructions responsive to the request;   a plurality of hardware units coupled to receive and execute the instructions to generate the response, each instruction designated for one of the plurality of hardware units; and   a memory coupled to the hardware units.   
     
     
         11 . The lattice-based cryptography engine of  claim 10  wherein the controller comprises:
 a read only memory (ROM) storing the instructions; 
 a sequencer coupled to the ROM; and 
 an instruction decode coupled to the sequencer. 
 
     
     
         12 . The lattice-based cryptography engine of  claim 11  and further comprising a program counter coupled to the sequencer. 
     
     
         13 . The lattice-based cryptography engine of  claim 11  wherein the ROM includes sets of instructions, each set corresponding to different cryptographic operations. 
     
     
         14 . The lattice-based cryptography engine of  claim 13  wherein the cryptographic operations include key generation, signature generation, and signature verification. 
     
     
         15 . The lattice-based cryptography engine of  claim 10  wherein the hardware units comprise sampler units, NTT units, and auxiliary units. 
     
     
         16 . The lattice-based cryptography engine of  claim 15  wherein the sampler units include a rejection sampler unit, a rejection bounded sampler unit, and sample InBall unit. 
     
     
         17 . The lattice-based cryptography engine of  claim 15  wherein the auxiliary units include a MakeHint unit, a UseHint unit, and a HintSum unit. 
     
     
         18 . The lattice-based cryptography engine of  claim 17  wherein the auxiliary units further include a Pack unit, and Unpack unit, an Encode unit, a Decode unit, a Comp unit, a Decomp unit, and a Ck Norm unit. 
     
     
         19 . The lattice-based cryptography engine of  claim 15  and further including hashing units, a serial-in parallel-out memory, a Keccak unit, and a parallel-in serial-out memory. 
     
     
         20 . A lattice-based cryptography engine comprising:
 an interface configured to receive a lattice-based cryptographic operation request including corresponding operands;   a register map configured to store the operands and a response to a request identifying a cryptographic operation;   a controller coupled to receive the operands and output a sequence of instructions responsive to the request; and   a plurality of hardware units coupled to receive and execute the instructions to generate the response, each instruction designated for one of the plurality of hardware units.