Light-Emitting Transistor and Driving and Preparation Method Therefor, Display Panel, and Display Apparatus

Abstract

A light-emitting transistor is disposed on a base substrate and includes a gate layer, a first insulating layer, a source layer, a barrier layer, a light-emitting functional layer, and a drain layer arranged in sequence along a direction away from the base substrate. The source layer includes a first wire grid structure, the first wire grid structure includes a plurality of first conductive strips arranged at intervals, and the plurality of first conductive strips are parallel to each other. The barrier layer covers surfaces of the plurality of first conductive strips, and a surface of the barrier layer away from the base substrate is parallel to the base substrate.

1 . A light-emitting transistor, disposed on a base substrate and comprising a gate layer, a first insulating layer, a source layer, a barrier layer, a light-emitting functional layer, and a drain layer arranged in sequence along a direction away from the base substrate, wherein
 the source layer includes a first wire grid structure, the first wire grid structure includes a plurality of first conductive strips arranged at intervals, and the plurality of first conductive strips are parallel to each other; and   the barrier layer covers surfaces of the plurality of first conductive strips, and a surface of the barrier layer away from the base substrate is parallel to the base substrate.   
     
     
         2 . The light-emitting transistor according to  claim 1 , wherein the source layer further includes:
 a second wire grid structure, located between the first wire grid structure and the first insulating layer, and having a spacing from the first wire grid structure along a direction perpendicular to the base substrate, wherein the second wire grid structure includes a plurality of second conductive strips arranged at intervals, extension directions of the plurality of second conductive strips are parallel to each other, and the extension directions of the second conductive strips are parallel to extension directions of the first conductive strips, wherein   an orthographic projection of the second wire grid structure on the base substrate is non-overlapping with an orthographic projection of the first wire grid structure on the base substrate; and along an arrangement direction of the plurality of second conductive strips, the plurality of second conductive strips and the plurality of first conductive strips are arranged alternately.   
     
     
         3 . The light-emitting transistor according to  claim 2 , further comprising:
 a first template layer, disposed between the first insulating layer and the source layer, and including a plurality of first grooves arranged at intervals and first dividing portions each located between two adjacent first grooves;   wherein at least one first conductive strip is located on one of the first dividing portions, and at least one second conductive strip is located in one of the first grooves; and along the direction perpendicular to the base substrate, a depth of the first groove is greater than a thickness of the second conductive strip.   
     
     
         4 . The light-emitting transistor according to  claim 3 , wherein the source layer further includes:
 a first planar structure, located on the first template layer, and arranged around the first wire grid structure and the second wire grid structure, wherein both ends of at least one of the first conductive strips along an extension direction thereof are electrically connected to the first planar structure, and both ends of at least one of the second conductive strips along an extension direction thereof are electrically connected to the first planar structure.   
     
     
         5 . The light-emitting transistor according to  claim 4 , wherein the first groove includes two first side walls disposed opposite each other along an extension direction of the first groove, ends of the first side walls away from the base substrate are connected to the first planar structure, and the at least one second conductive strip covers the first side walls and is connected to a portion of the first planar structure located at both ends of the first groove; or
 the first groove includes two first side walls disposed opposite each other along an extension direction of the first groove, ends of the first side walls away from the base substrate are connected to the first planar structure, and the at least one second conductive strip covers the first side walls and is connected to a portion of the first planar structure located at both ends of the first groove; and the first groove further includes two second side walls disposed opposite each other along an arrangement direction of the plurality of first grooves; and an included angle between the second side walls and a reference plane is greater than an included angle between the first side walls and the reference plane, the reference plane being parallel to the base substrate.   
     
     
         6 . (canceled) 
     
     
         7 . The light-emitting transistor according to  claim 4 , wherein the light-emitting transistor has a light-emitting region and a non-light-emitting region surrounding the light-emitting region; and
 the first wire grid structure and the second wire grid structure are located in the light-emitting region, and the first planar structure covers the non-light-emitting region.   
     
     
         8 . The light-emitting transistor according to  claim 4 , further comprising:
 a connecting metal block, disposed between the base substrate and the gate layer, and configured to transmit a voltage signal to the source layer;   a second insulating layer, disposed between the connecting metal block and the source layer; and   a first via hole, extending through the first template layer, the first insulating layer and the second insulating layer along the direction perpendicular to the base substrate, wherein a side wall of the first via hole has at least one step structure;   wherein the source layer further includes a connection structure, the connection structure covers the side wall and a bottom of the first via hole and is electrically connected to the connecting metal block, and the connection structure is connected to the first planar structure at a distal end thereof.   
     
     
         9 . The light-emitting transistor according to  claim 8 , wherein
 an opening of the first via hole on a surface of the first template layer away from the base substrate is in a long strip shape; and an extension direction of the opening is parallel to an extension direction of the first groove, or the extension direction of the opening is at an included angle to the extension direction of the first groove; or   there are a plurality of first via holes, and the plurality of first via holes are arranged in multiple rows along the extension directions of the first conductive strips, with at least one of the first via holes in each row; or   the first groove further includes two second side walls disposed opposite each other; and the first via hole includes a first sub-via hole located within the first template layer, and an included angle between a side wall of the first sub-via hole and a reference plane is less than an included angle between the second side walls and the reference plane, the reference plane being parallel to the base substrate.   
     
     
         10 . (canceled) 
     
     
         11 . (canceled) 
     
     
         12 . The light-emitting transistor according to  claim 1 , wherein
 along a direction perpendicular to an extension direction of a first conductive strip, a width of the first conductive strip is W 1 , a pitch between two adjacent first conductive strips is P 1 , and W 1 /P 1  ranges from 0.3 to 0.6.   
     
     
         13 . (canceled) 
     
     
         14 . The light-emitting transistor according to  claim 1 , wherein
 the barrier layer includes an active layer, the active layer covers side walls of the first conductive strips and surfaces of the first conductive strips away from the base substrate, and a surface of the active layer away from the base substrate is parallel to the base substrate.   
     
     
         15 . The light-emitting transistor according to  claim 14 , further comprising a second wire grid structure located between the first wire grid structure and the first insulating layer, and including a plurality of second conductive strips arranged at intervals, extension directions of the second conductive strips being parallel to extension directions of the first conductive strips, wherein the active layer further covers surfaces of second conductive strips. 
     
     
         16 . (canceled) 
     
     
         17 . The light-emitting transistor according to  claim 1 , wherein the barrier layer includes:
 an active layer, covering surfaces of the first conductive strips away from the base substrate and exposing at least a portion of side walls of the first conductive strips, wherein a surface of the active layer away from the base substrate has a high and low undulating profile; and   a hole injection layer, located on a side of the active layer away from the base substrate, and covering the side walls of the first conductive strips and the surface of the active layer, wherein a surface of the hole injection layer away from the base substrate is parallel to the base substrate.   
     
     
         18  . . . (Currently Amended) The light-emitting transistor according to  claim 1 , wherein the light-emitting transistor is a light-emitting region and a non-light-emitting region; the light-emitting transistor is a top-emission light-emitting transistor, and the light-emitting transistor further comprises:
 an auxiliary electrode, disposed on a side of the drain layer away from the base substrate and electrically connected to the drain layer, wherein the auxiliary electrode includes a third wire grid structure located in the light-emitting region, and the third wire grid structure includes a plurality of third conductive strips arranged at intervals, and the plurality of third conductive strips are parallel to each other. 
 
     
     
         19 . (canceled) 
     
     
         20 . The light-emitting transistor according to  claim 18 , further comprising:
 a second template layer, disposed between the drain layer and the auxiliary electrode, and located in the light-emitting region, wherein the second template layer includes a plurality of second grooves arranged at intervals, and second dividing portions each located between two adjacent second grooves; at least one third conductive strip is located in one of the second grooves, and along a direction perpendicular to the base substrate, a depth of the second groove is greater than a thickness of the third conductive strip;   wherein the auxiliary electrode further includes a fourth wire grid structure, the fourth wire grid structure includes a plurality of fourth conductive strips arranged at intervals, the plurality of fourth conductive strips are parallel to each other, and the plurality of fourth conductive strips are parallel to the plurality of third conductive strips; and at least one fourth conductive strip is located on one of the second dividing portions.   
     
     
         21 . The light-emitting transistor according to  claim 20 , wherein the auxiliary electrode further includes a second planar structure, the second planar structure is located in the non-light-emitting region, and at least a portion of the second planar structure is in direct contact with the drain layer; the second planar structure surrounds the plurality of third conductive strips and the plurality of fourth conductive strips, and ends of the plurality of third conductive strips and ends of the plurality of fourth conductive strips are electrically connected to the second planar structure, independently. 
     
     
         22 . (canceled) 
     
     
         23 . A display panel, comprising:
 a base substrate and a driving circuit disposed on the base substrate; and   light-emitting transistors each according to  claim 1 , the light-emitting transistors being disposed on a side of the driving circuit away from the base substrate;   wherein a gate layer of a light-emitting transistor is electrically connected to the driving circuit, and the driving circuit is configured to transmit a voltage signal to the gate layer according to a gray scale to be displayed by the light-emitting transistor.   
     
     
         24 . The display panel according to  claim 23 , wherein the display panel comprises a plurality of sub-pixels, each sub-pixel including one of the light-emitting transistors; and extension directions of first conductive strips of at least two light-emitting transistors intersect with each other. 
     
     
         25 . A display apparatus, comprising the display panel according to  claim 23 . 
     
     
         26 . A driving method for a light-emitting transistor, the driving method comprising:
 applying a positive voltage to a source layer of the light-emitting transistor, and applying a negative voltage to a drain layer of the light-emitting transistor; and   adjusting a voltage on a gate layer of the light-emitting transistor according to a gray scale to be displayed by the light-emitting transistor, wherein the voltage on the gate layer is positively correlated with a current flowing through the light-emitting transistor.   
     
     
         27 . A manufacturing method for a light-emitting transistor, the manufacturing method comprising:
 forming a gate layer and a first insulating layer in sequence on a side of a base substrate;   forming a source layer on a side of the first insulating layer away from the base substrate, wherein the source layer includes a first wire grid structure, the first wire grid structure includes a plurality of first conductive strips arranged at intervals, and the plurality of first conductive strips are parallel to each other; and   forming a barrier layer on a side of the source layer away from the base substrate, wherein the barrier layer covers surfaces of the first conductive strips of the source layer, and a surface of the barrier layer away from the base substrate is parallel to the base substrate.   
     
     
         28 - 30 . (canceled)