Discrete power transistor configured with enhanced harmonic termination and process of implementing the same

Abstract

A packaged transistor device includes an RF signal input lead, an RF signal output lead, and a discrete transistor having a transistor structure arranged and/or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and/or formed on the substrate of the discrete transistor.

1 . A packaged transistor device comprising:
 an RF signal input lead;   an RF signal output lead;   a discrete transistor comprising a transistor structure arranged and/or formed on a substrate; and   at least one harmonic reduction circuit arranged and/or formed on the substrate of the discrete transistor.   
     
     
         2 . The packaged transistor device according to  claim 1 , wherein the discrete transistor is configured to connect the at least one harmonic reduction circuit to a control electrode of the transistor structure. 
     
     
         3 . The packaged transistor device according to  claim 1 , wherein the at least one harmonic reduction circuit is coupled to an output electrode of the transistor structure. 
     
     
         4 . The packaged transistor device according to  claim 1 , wherein the substrate comprises silicon carbide (SiC). 
     
     
         5 . (canceled) 
     
     
         6 . The packaged transistor device according to  claim 1 , further comprising an input matching circuit and/or an output matching circuit. 
     
     
         7 . The packaged transistor device according to  claim 1 , wherein a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and/or is arranged at least partially on the substrate and the transistor structure. 
     
     
         8 . The packaged transistor device according to  claim 1 , wherein a structure of the transistor structure is arranged at least partially on the substrate and/or is arranged at least partially on the at least one harmonic reduction circuit. 
     
     
         9 . The packaged transistor device according to  claim 1 , wherein the at least one harmonic reduction circuit comprises at least one inductive element, at least one capacitor, and/or at least one resistor. 
     
     
         10 . The packaged transistor device according to  claim 9 ,
 wherein the at least one capacitor comprises at least one dielectric layer, at least one capacitor top metal, at least one capacitor bottom metal; and   wherein the at least one capacitor forms a capacitor with the at least one capacitor top metal and the at least one capacitor bottom metal having the at least one dielectric layer therebetween.   
     
     
         11 . The packaged transistor device according to  claim 9 , wherein a structure of the at least one capacitor is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and/or is arranged at least partially on the substrate and the transistor structure. 
     
     
         12 . The packaged transistor device according to  claim 9 ,
 wherein the at least one inductive element comprises at least one inductor metal; and   wherein the at least one inductive element forms an inductor by arrangement of the at least one inductor metal on the substrate of the discrete transistor.   
     
     
         13 . The packaged transistor device according to  claim 9 , wherein a structure of the at least one inductive element comprises at least one inductor metal arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and/or is arranged at least partially on the substrate and the transistor structure. 
     
     
         14 . The packaged transistor device according to  claim 9 , wherein a structure of the at least one inductive element is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, is arranged at least partially on the substrate and the transistor structure, and/or is arranged at least partially on the at least one capacitor. 
     
     
         15 - 18 . (canceled) 
     
     
         19 . The packaged transistor device according to  claim 9 , wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor. 
     
     
         20 . The packaged transistor device according to  claim 9 ,
 wherein the at least one capacitor is buried underneath one or more bond pads of the discrete transistor; and   wherein the at least one inductive element is arranged in a whitespace of the transistor structure.   
     
     
         21 . The packaged transistor device according to  claim 9 ,
 wherein the at least one capacitor is arranged in a whitespace of the transistor structure; and   wherein the at least one inductive element is arranged in a whitespace of the transistor structure.   
     
     
         22 . The packaged transistor device according to  claim 9 , wherein the at least one inductive element is between implementations of one or more bond pads of the discrete transistor. 
     
     
         23 - 33 . (canceled) 
     
     
         34 . The packaged transistor device according to  claim 1 , further comprising:
 an over-mold configuration;   a support component; and   one or more interconnects coupled to the discrete transistor, an input matching circuit, an output matching circuit, the RF signal output lead, and/or the RF signal input lead.   
     
     
         35 . A process of implementing a packaged transistor device comprising:
 providing an RF signal input lead;   providing an RF signal output lead;   forming and arranging a discrete transistor comprising a transistor structure on a substrate; and   forming and arranging at least one harmonic reduction circuit on the substrate of the discrete transistor.   
     
     
         36 - 68 . (canceled) 
     
     
         69 . A packaged transistor device comprising:
 an RF signal input lead;   an RF signal output lead;   a discrete transistor comprising a transistor structure arranged and/or formed on a substrate; and   at least one harmonic reduction circuit arranged and/or formed on the substrate of the discrete transistor,   wherein a structure of the at least one harmonic reduction circuit is arranged at least partially on the substrate, is arranged at least partially on the transistor structure, and/or is arranged at least partially on the substrate and the transistor structure.   
     
     
         70 - 134 . (canceled)