Chip module having contact surface with dual-layer protective coating

Abstract

A chip module having a contact surface for contact-based communication with a reader, where the contact surface includes a metal, and a coating of the contact surface with a double layer composed of a lower layer of an organic silicon compound and/or a carbon compound and an upper layer of silicon oxide, wherein the double layer has a thickness that has an electrical surface contact resistance of not more than 500 mO according to ISO 7810 when measured in accordance with ISO 10373-1.

1 . A chip module, comprising:
 a contact surface for contact-based communication with a reader, where the contact surface includes a metal; and   a coating of the contact surface with a double layer composed of a lower layer of an organic silicon compound and/or a carbon compound and an upper layer of silicon oxide,   wherein the double layer has a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1.   
     
     
         2 . The chip module as claimed in  claim 1 ,
 wherein the contact surface includes a gold layer as a top metal layer that forms a common interface with the lower layer.   
     
     
         3 . The chip module as claimed in  claim 2 ,
 wherein the gold layer has a layer thickness within a range of less than 20 nm.   
     
     
         4 . The chip module as claimed in  claim 1 ,
 wherein the upper layer has a layer thickness within a range from about 75 nm to about 85 nm.   
     
     
         5 . The chip module as claimed in  claim 1 ,
 wherein the upper layer has been produced by plasma coating.   
     
     
         6 . The chip module as claimed in  claim 1 ,
 wherein the double layer has a layer thickness within a range from about 90 nm to about 200 nm.   
     
     
         7 . The chip module as claimed in  claim 1 ,
 wherein the lower layer has been produced using a coating process from a group of coating processes consisting of: wet-chemical coating by immersion; free-jet plasma coating;   chemical vapor deposition; hot-wire-activated vapor deposition; and physical vapor deposition.   
     
     
         8 . The chip module as claimed in  claim 1 ,
 wherein the organic silicon compound includes a compound selected from a group consisting of: Si—O, Si—N, Si—C, Si—OH, and Si—H.   
     
     
         9 . The chip module as claimed in  claim 1 ,
 wherein the organic silicon compound includes a compound selected from a group consisting of: organosilane, organosilanol, organochlorosilane, siloxane, silicone, polysilazane, and carbosilane; and/or   wherein the carbon compound includes a compound selected from a group consisting of: amorphous carbon, diamond, graphene, and graphite.   
     
     
         10 . A process for producing a chip module, the process comprising:
 coating a contact surface for contact-based communication with a reader including a metal with a lower layer of an organic silicon compound and/or a carbon compound; and   coating the lower layer with an upper layer of silicon oxide, where the double layer of the lower and upper layers has a thickness that has an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured in accordance with ISO 10373-1 ( 320 ).   
     
     
         11 . The process as claimed in  claim 10 ,
 wherein the contact surface includes a gold layer as a top metal layer that forms a common interface with the lower layer.   
     
     
         12 . The process as claimed in  claim 11 ,
 wherein the gold layer has a layer thickness within a range of less than 20 nm.   
     
     
         13 . The process as claimed in  claim 10 ,
 wherein the upper layer has a layer thickness within a range from about 75 nm to about 85 nm.   
     
     
         14 . The process as claimed in  claim 10 ,
 wherein the upper layer has been produced by plasma coating.   
     
     
         15 . The process as claimed in  claim 10 ,
 wherein the double layer has a layer thickness within a range from about 90 nm to about 200 nm.   
     
     
         16 . The process as claimed in  claim 10 ,
 wherein the lower layer has been created using a coating process selected from a group of coating processes consisting of: wet-chemical coating by immersion, free-jet plasma coating, chemical vapor deposition, hot-wire-activated vapor deposition, and physical vapor deposition.   
     
     
         17 . The process as claimed in  claim 10 ,
 wherein the organic silicon compound includes a compound selected from a group consisting of: Si—O, Si—N, Si—C, Si—OH, and Si—H.   
     
     
         18 . The process as claimed in  claim 10 ,
 wherein the organic silicon compound includes a compound selected from a group consisting of: organosilane, organosilanol, organochlorosilane, siloxane, silicone, polysilazane, and carbosilane; and/or   wherein the carbon compound includes a compound selected from a group consisting of: amorphous carbon, diamond, graphene, and graphite.