Structure with high voltage transistor, middle voltage transistor and low voltage transistor and fabricating method of the same

Abstract

A structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor includes a substrate. The substrate includes a high voltage region, a middle voltage region and a low voltage region. A high voltage transistor is disposed within in the high voltage region. The high voltage transistor includes a first gate dielectric layer embedded in the substrate, and a first gate structure disposed on the first gate dielectric layer. A middle voltage transistor is disposed in the middle voltage region. The middle voltage transistor includes a second gate dielectric layer embedded in the substrate. A second gate structure is disposed on the second gate dielectric layer, wherein a thickness of the second gate structure is greater than a thickness of the first gate structure.

What is claimed is: 
     
         1 . A structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor, comprising:
 a substrate, wherein the substrate comprises a high voltage region, a middle voltage region and a low voltage region;   a high voltage transistor disposed in the high voltage region, wherein the high voltage transistor comprises a first gate dielectric layer embedded in the substrate and a first gate structure disposed on the first gate dielectric layer;   a middle voltage transistor disposed in the middle voltage region, wherein the middle voltage transistor comprises a second gate dielectric layer embedded in the substrate, and a second gate structure disposed on the second gate dielectric layer;   a low voltage transistor disposed in the low voltage region, wherein the low voltage transistor comprises a fin structure protruding from a first surface of the substrate, and a third gate structure covering and crossing the fin structure; and   a shallow trench insulation (STI) covering the first surface of the substrate in the low voltage region and disposed at one side of the fin structure, wherein the fin structure protrudes from the STI, and a top surface of the STI is aligned with a top surface of the second gate dielectric layer.   
     
     
         2 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 1 , wherein the high voltage region of the substrate has a second surface, the middle voltage region of the substrate has a third surface, the second surface is higher than the third surface, and the first surface is lower than the third surface. 
     
     
         3 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 2 , wherein a top surface of the first gate dielectric layer is aligned with the second surface, and the top surface of the second gate dielectric layer is aligned with the third surface. 
     
     
         4 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 1 , further comprising:
 two first deep trench isolations embedded in the high voltage region of the substrate, wherein the two first deep trench isolations are respectively disposed at two sides of the first gate dielectric layer and connected to the first gate dielectric layer; and   two second deep trench isolations embedded in the middle voltage region of the substrate, wherein the two second deep trench isolations are respectively disposed at two sides of the second gate dielectric layer.   
     
     
         5 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 4 , further comprising:
 two doping regions respectively disposed in the substrate at two sides of the first gate dielectric layer; and   two silicides respectively disposed in the substrate at two sides of the second gate dielectric layer, wherein each of the two silicides is disposed between one of the two second deep trench isolations and the second gate dielectric layer.   
     
     
         6 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 1 , wherein a thickness of the third gate structure and a thickness of the second gate structure are the same. 
     
     
         7 . A structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor, comprising:
 a substrate, wherein the substrate comprises a high voltage region, a middle voltage region and a low voltage region;   a high voltage transistor disposed in the high voltage region, wherein the high voltage transistor comprises a first gate dielectric layer embedded in the substrate and a first gate structure disposed on the first gate dielectric layer; and   a middle voltage transistor disposed in the middle voltage region, wherein the middle voltage transistor comprises a second gate dielectric layer embedded in the substrate, and a second gate structure disposed on the second gate dielectric layer, wherein a thickness of the second gate structure is greater than a thickness of the first gate structure.   
     
     
         8 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 7 , further comprising:
 a low voltage transistor disposed in the low voltage region, wherein the low voltage transistor comprises a fin structure protruding from a first surface of the substrate, and a third gate structure covering and crossing the fin structure; and   a shallow trench insulation (STI) covering the first surface of the substrate in the low voltage region and disposed at one side of the fin structure.   
     
     
         9 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 8 , wherein the high voltage region of the substrate has a second surface, the middle voltage region of the substrate has a third surface, the second surface is higher than the third surface, and the first surface is lower than the third surface. 
     
     
         10 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 9 , wherein a top surface of the first gate dielectric layer is aligned with the second surface, and a top surface of the second gate dielectric layer is aligned with the third surface. 
     
     
         11 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 7 , further comprising:
 two first deep trench isolations embedded in the high voltage region of the substrate, wherein the two first deep trench isolations are respectively disposed at two sides of the first gate dielectric layer and connected to the first gate dielectric layer; and   two second deep trench isolations embedded in the middle voltage region of the substrate, wherein the two second deep trench isolations are respectively disposed at two sides of the second gate dielectric layer.   
     
     
         12 . The structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 11 , further comprising:
 two doping regions respectively disposed in the substrate at two sides of the first gate dielectric layer; and   two silicides respectively disposed in the substrate at two sides of the second gate dielectric layer, wherein each of the two silicides is disposed between one of the two second deep trench isolations and the second gate dielectric layer.   
     
     
         13 . A fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor, comprising:
 providing a substrate, wherein the substrate comprises a high voltage region, a middle voltage region and a low voltage region, and wherein the low voltage region of the substrate has a first surface, at least one fin structure protrudes from the first surface, a shallow trench insulation (STI) is disposed at one side of the fin structure, two first deep trench isolations are embedded in the substrate of the high voltage region, two second deep trench isolations are embedded in the substrate of the middle voltage region, the high voltage region of the substrate has a second surface, and the middle voltage region of the substrate has a third surface, the second surface and the third surface are aligned, and the first surface is lower than the second surface;   etching the first surface and the second surface to form a first trench and a second trench, wherein the first trench is disposed between the two first deep trench isolations and the second trench is disposed between the two second deep trench isolations;   forming a first silicon oxide layer and a second silicon oxide layer respectively filling the first trench and the second trench, wherein the first silicon oxide layer and the second silicon oxide layer are aligned;   removing part of the second silicon oxide layer to make a top surface of the second silicon oxide layer lower than a top surface of the first silicon oxide layer;   removing part of the STI to expose part of the fin structure; and   after removing part of the second silicon oxide layer, forming a first gate structure, a second gate structure and a third gate structure to respectively cover the first silicon oxide layer, the second silicon oxide layer and the fin structure.   
     
     
         14 . The fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 13 , wherein a depth of the first trench and a depth of the second trench are the same. 
     
     
         15 . The fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 13 , wherein the part of the second silicon oxide layer and the part of the STI are both removed by the same etching back process. 
     
     
         16 . The fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 15 , wherein after the etching back process, the top surface of the second silicon oxide layer is aligned with a top surface of the STI. 
     
     
         17 . The fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 13 , wherein a thickness of the second gate structure is greater than a thickness of the first gate structure. 
     
     
         18 . The fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 13 , further comprising before forming the first trench and the second trench, forming two lightly doping regions in the substrate between the two second deep trench isolations. 
     
     
         19 . The fabricating method of a structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor of  claim 13 , further comprising before removing the part of the second silicon oxide layer, forming two lightly doping regions in the substrate between the two second deep trench isolations.