US2026013160A1PendingUtilityA1

Semiconductor device

Assignee: ROHM CO LTDPriority: Mar 16, 2023Filed: Sep 9, 2025Published: Jan 8, 2026
Est. expiryMar 16, 2043(~16.6 yrs left)· nominal 20-yr term from priority
Inventors:TAKIGAWA Yuto
H10D 12/021H10D 8/60H10D 62/103H10D 62/126H10D 12/212H10W 10/10H10W 10/011H10W 10/00H10W 10/01H10D 8/051H10D 62/106H10D 62/8325H10D 8/605
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Claims

Abstract

A semiconductor device includes an n-type semiconductor layer, trenches, an insulating layer, a third electrode, and a p-type well region. The trenches extend in a first direction orthogonal to the thickness direction of the semiconductor layer and are spaced apart in a second direction orthogonal to the first direction. The insulating layer covers the trenches. The third electrode is formed in the insulating layer in contact with the first electrode. The well region is formed in the surface of the semiconductor layer. The well region extends in a direction intersecting the first direction and is one well regions spaced apart in the first direction. The surface of the semiconductor layer is in ohmic contact with the first electrode at the well surface of the well region. The surface of the semiconductor layer is in Schottky contact with the first electrode at an exposed surface between the well surfaces.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate of a first conductive type including a substrate front surface and a substrate back surface opposite the substrate front surface;   a semiconductor layer of the first conductive type formed on the semiconductor front surface and including a surface;   a first electrode formed on the surface of the semiconductor layer;   a second electrode formed on the substrate back surface;   trenches extending in a thickness direction of the semiconductor layer from the surface of the semiconductor layer and extending in a first direction that is orthogonal to the thickness direction of the semiconductor layer, wherein the trenches are spaced apart in a second direction that is orthogonal to the thickness direction of the semiconductor layer and to the first direction;   an insulating layer covering a bottom wall and side walls of each of the trenches;   a third electrode formed in the insulating layer and contacting the first electrode; and   a well region of a second conductive type formed in a part of the surface of the semiconductor layer, wherein   the well region is one of multiple well regions extending in a direction intersecting the first direction and spaced apart in the first direction;   the well region includes a well surface forming a part of the surface of the semiconductor layer and well ends contacting the insulating layer of one of the trenches, wherein the well surface is one of multiple well surfaces, and   the surface of the semiconductor layer is in ohmic contact with the first electrode at the well surfaces, and the surface of the semiconductor layer is in Schottky contact with the first electrode at an exposed surface located between the multiple well surfaces.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the well region extends in a direction intersecting the first direction and spans across one of the trenches without overlapping with the one of the trenches. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the well region extends in the second direction. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the multiple wells regions are spaced apart at equal intervals in the first direction. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein a total area (S 1 ) of the well surfaces is less than a total area (S 2 ) of the exposed surface. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein an area ratio (S 1 /S 2 ) of a total area (S 1 ) of the well surfaces to a total area (S 2 ) of the exposed surface satisfies 0<S 1 /S 2 ≤100. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein a total area (S 1 ) of the well surfaces is greater than a total area (S 2 ) of the exposed surface. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein an area ratio (S 1 /S 2 ) of the total area (S 1 ) of the well surfaces to the total area (S 2 ) of the exposed surface satisfies 1<S 1 /S 2 ≤100. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein a first direction length of the well surface is less than a distance between adjacent ones of the trenches. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein a first direction length of the well surface is greater than a distance between adjacent ones of the trenches. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein a first direction length of the well surface is greater than a second direction length of one of the trenches. 
     
     
         12 . The semiconductor device according to  claim 1 , wherein a thickness of the well region is less than or equal to one-half of a depth of one of the trenches. 
     
     
         13 . The semiconductor device according to  claim 1 , wherein the insulating layer of one of the trenches includes:
 first parts contacting the well ends of the well region; and   a second part contacting the semiconductor layer and located between the first parts.

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