Enhanced back via landing metal layer adhesion

Abstract

Landing metal layers with improved adhesion to semiconductor substrates are described, along with semiconductor structures including the landing metal layers and components using the landing metal layers. An example semiconductor device includes a substrate with top and bottom surfaces, a landing metal layer over the top surface of the substrate, a via that extends through the substrate, and a bottom side metal layer. The bottom side metal layer extends over sidewalls of the via and electrically contacts an underside of the landing metal layer. For improved adhesion, the landing metal layer is diffused at least in part into the top surface of the substrate. The landing metal layer is diffused into the top surface of the substrate by an annealing or alloying process, and the techniques described herein help to avoid the delamination of the landing metal layer from the top surface of the substrate.

Therefore, at least the following is claimed: 
     
         1 . A semiconductor structure comprising:
 a substrate comprising a top surface and a bottom surface;   a landing metal layer on and diffused at least in part into the top surface of the substrate;   a via that extends through from the bottom surface to the top surface of the substrate; and   a bottom side metal layer over the bottom surface of the substrate, over sidewalls of the via, and that electrically contacts an underside of the landing metal layer.   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein:
 the landing metal layer comprises a stack of metal layers; and   the stack of metal layers comprises a base metal layer of one of platinum, palladium, zinc, magnesium, titanium, nickel, tantalum, aluminum, or chromium on and diffused at least in part into the top surface of the substrate.   
     
     
         3 . The semiconductor structure according to  claim 1 , wherein:
 the landing metal layer comprises a stack of metal layers; and   the stack of metal layers comprises a platinum layer on and diffused at least in part into the top surface of the substrate, a titanium layer, a second platinum layer, a gold layer, and a second titanium layer.   
     
     
         4 . The semiconductor structure according to  claim 1 , further comprising:
 an insulating layer over the landing metal layer; and   a second metal layer over the insulating layer.   
     
     
         5 . The semiconductor structure according to  claim 4 , wherein the landing metal layer, the insulating layer, and the second metal layer comprise a metal-insulator-metal (MIM) capacitor. 
     
     
         6 . The semiconductor structure according to  claim 4 , wherein:
 the landing metal layer comprises a base metal layer of one of platinum, palladium, zinc, or magnesium on and diffused at least in part into the top surface of the substrate; and   the second metal layer comprises a titanium layer on the insulating layer.   
     
     
         7 . The semiconductor structure according to  claim 4 , wherein the second metal layer is electrically coupled to a contact of an active semiconductor device by an interconnect metal layer. 
     
     
         8 . The semiconductor structure according to  claim 4 , wherein the second metal layer is electrically coupled to a contact of an active semiconductor device by a metal air bridge. 
     
     
         9 . The semiconductor structure according to  claim 1 , wherein the landing metal layer comprises a metal layer for a capacitor, an inductor, or a bond pad. 
     
     
         10 . A semiconductor structure comprising:
 a landing metal layer on and diffused at least in part into a top surface of a substrate;   a via that extends through from a bottom surface to the top surface of the substrate under the landing metal layer; and   a bottom side metal layer in the via and that electrically contacts an underside of the landing metal layer.   
     
     
         11 . The semiconductor structure according to  claim 10 , wherein the landing metal layer comprises a base meal layer of one of platinum, palladium, zinc, magnesium, titanium, nickel, tantalum, aluminum, or chromium on and diffused at least in part into a top surface of a substrate. 
     
     
         12 . The semiconductor structure according to  claim 10 , further comprising:
 an insulating layer over the landing metal layer; and   a second metal layer over the insulating layer.   
     
     
         13 . The semiconductor structure according to  claim 12 , wherein the landing metal layer, the insulating layer, and the second metal layer comprise a metal-insulator-metal (MIM) capacitor. 
     
     
         14 . The semiconductor structure according to  claim 12 , wherein:
 the landing metal layer consists of a stack of aplatinum layer on and diffused at least in part into a top surface of a substrate, a titanium layer over the platinum layer, a second platinum layer over the titanium layer, a gold layer over the second platinum layer, and a second titanium layer over the gold layer; and   the second metal layer comprises a titanium layer on the insulating layer.   
     
     
         15 . The semiconductor structure according to  claim 12 , wherein the second metal layer is electrically coupled to a contact of an active semiconductor device by an interconnect metal layer. 
     
     
         16 . The semiconductor structure according to  claim 12 , wherein the second metal layer is electrically coupled to a contact of an active semiconductor device by a metal air bridge. 
     
     
         17 . A process for manufacturing a landing metal layer, comprising:
 providing a substrate comprising a top surface and a bottom surface;   depositing a landing metal layer over the top surface of the substrate;   annealing the landing metal layer to diffuse the landing metal layer at least in part into the top surface of the substrate;   etching a via opening through from the bottom surface to the top surface of the substrate; and   depositing a bottom side metal layer over the bottom surface of the substrate, over sidewalls of the via, and that electrically contacts an underside of the landing metal layer.   
     
     
         18 . The process according to  claim 17 , further comprising:
 before the etching and after the annealing, forming an insulating layer over the landing metal layer; and   depositing a second metal layer over the insulating layer.   
     
     
         19 . The process according to  claim 18 , wherein the landing metal layer, the insulating layer, and the second metal layer comprise a metal-insulator-metal (MIM) capacitor. 
     
     
         20 . The process according to  claim 18 , wherein the landing metal layer comprises a base metal layer of one of platinum, palladium, zinc, magnesium, titanium, nickel, tantalum, aluminum, or chromium on and diffused at least in part into the top surface of the substrate.