Power and signal distribution in stacked semiconductor systems

Abstract

Methods, systems, and devices for power and signal distribution in stacked semiconductor systems are described. A semiconductor system may include a distribution component configured to communicate power, signals, or both with a logic component and memory component(s) of the semiconductor system. The distribution component may include power delivery circuitry to provide separate power to the memory component(s) and the logic component, data serialization/deserialization circuitry to communicate data signals with the logic component, or both. The distribution component may convey power, data signals, or both to the logic component using conductive vias that pass through the memory components and bypass interface circuitry of the memory component(s). The distribution component may include clock circuitry that receives, generates, or both, one or more clock signals and provides the one or more clock signals for I/O functionality of the distribution component, the logic component, the interface circuitry, or any combination thereof.

What is claimed is: 
     
         1 . A semiconductor system, comprising:
 one or more first semiconductor components comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays,   a second semiconductor component bonded with a first side of the one or more first semiconductor components, the second semiconductor component comprising logic circuitry that is coupled with the interface circuitry; and   a third semiconductor component bonded with a second side of the one or more first semiconductor components, the third semiconductor component comprising first power delivery circuitry having a first output that is coupled with the interface circuitry and comprising second power delivery circuitry having a second output that is coupled with the logic circuitry.   
     
     
         2 . The semiconductor system of  claim 1 , wherein the first output of the first power delivery circuitry is electrically isolated from the second output of the second power delivery circuitry. 
     
     
         3 . The semiconductor system of  claim 2 , wherein the first output of the first power delivery circuitry is associated with a different voltage, a different current, or both compared with the second output of the second power delivery circuitry. 
     
     
         4 . The semiconductor system of  claim 1 , further comprising:
 one or more conductive vias extending through the one or more first semiconductor components and bypassing the interface circuitry, the second output of the second power delivery circuitry coupled with the logic circuitry through the one or more conductive vias.   
     
     
         5 . The semiconductor system of  claim 1 , wherein the third semiconductor component comprises one or more conductive contacts at a surface of the third semiconductor component opposite the one or more first semiconductor components, the one or more conductive contacts configured to receive power and being coupled with a first input of the first power delivery circuitry and with a second input of the second power delivery circuitry. 
     
     
         6 . The semiconductor system of  claim 1 , wherein the third semiconductor component comprises one or more conductive contacts at a surface of the third semiconductor component opposite the one or more first semiconductor components and configured to communicate control signaling associated with the first power delivery circuitry, the second power delivery circuitry, or both. 
     
     
         7 . The semiconductor system of  claim 1 , wherein the third semiconductor component comprises circuitry operable to enable or disable power delivery from the first output of the first power delivery circuitry, from the second output of the second power delivery circuitry, or both. 
     
     
         8 . The semiconductor system of  claim 1 , wherein the third semiconductor component comprises clock circuitry having one or more first outputs coupled with the logic circuitry, one or more second outputs coupled with interface circuitry, or both, the clock circuitry configured to output one or more clock signals based on an oscillator of the clock circuitry, based on one or more received clock signals, or a combination thereof. 
     
     
         9 . The semiconductor system of  claim 1 , wherein the bonding of the second semiconductor component with the first side of the one or more first semiconductor components, the bonding of the third semiconductor component with the second side of the one or more first semiconductor components, or both include a fusion of dielectric material portions and a fusion of conductive material portions. 
     
     
         10 . A method for operating a semiconductor system, comprising:
 outputting first power from first power delivery circuitry of a third semiconductor component to interface circuitry of one or more first semiconductor components, the third semiconductor component bonded with a first side of the one or more first semiconductor components, and the interface circuitry for accessing one or more memory arrays of the one or more first semiconductor components; and   outputting second power from second power delivery circuitry of the third semiconductor component to logic circuitry of a second semiconductor component, the second semiconductor component bonded with a second side of the one or more first semiconductor components, and the logic circuitry coupled with the interface circuitry and operable to access the one or more memory arrays via the interface circuitry.   
     
     
         11 . The method of  claim 10 , wherein:
 the first power is output from a first output of the first power delivery circuitry; and   the second power is output from a second output of the second power delivery circuitry that is electrically isolated from the first output.   
     
     
         12 . The method of  claim 11 , wherein the first power is associated with a different voltage, a different current, or both from the second power. 
     
     
         13 . The method of  claim 10 , further comprising:
 receiving power through one or more conductive contacts at a surface of the third semiconductor component opposite the one or more first semiconductor components, wherein the first power and the second power are output based on the received power.   
     
     
         14 . The method of  claim 10 , further comprising:
 communicating control signaling through one or more conductive contacts at a surface of the third semiconductor component opposite the one or more first semiconductor components the control signaling associated with the first power delivery circuitry, the second power delivery circuitry, or both.   
     
     
         15 . A method of forming a semiconductor apparatus, comprising:
 bonding a third semiconductor component with a first side of one or more first semiconductor components, the one or more first semiconductor components comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays, and bonding the third semiconductor component with the first side of the one or more first semiconductor components comprising coupling a first output of first power delivery circuitry of the third semiconductor component with the interface circuitry; and   bonding a second semiconductor component with a second side of the one or more first semiconductor components, the second semiconductor component comprising logic circuitry, and bonding the second semiconductor component with the second side of the one or more first semiconductor components comprising coupling the logic circuitry with the interface circuitry and coupling a second output of second power delivery circuitry of the third semiconductor component with the logic circuitry.   
     
     
         16 . The method of  claim 15 , wherein the first output of the first power delivery circuitry is electrically isolated from the second output of the second power delivery circuitry. 
     
     
         17 . The method of  claim 15 , further comprising:
 forming one or more conductive vias extending through the one or more first semiconductor components and bypassing the interface circuitry, the second output of the second power delivery circuitry coupled with the logic circuitry through the one or more conductive vias.   
     
     
         18 . The method of  claim 15 , wherein the bonding of the second semiconductor component with the first side of the one or more first semiconductor components, the bonding of the third semiconductor component with the second side of the one or more first semiconductor components, or both comprise a fusion of dielectric material portions and a fusion of conductive material portions. 
     
     
         19 . A semiconductor system, comprising:
 one or more first semiconductor components comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays;   a second semiconductor component bonded with a first side of the one or more first semiconductor components, the second semiconductor component comprising a logic circuitry that is coupled with the interface circuitry; and   a third semiconductor component bonded with a second side of the one or more first semiconductor components, the third semiconductor component comprising serialization/deserialization circuitry having a first port that is coupled with the logic circuitry and a second port that is coupled with one or more conductive contacts at a surface of the third semiconductor component.   
     
     
         20 . The semiconductor system of  claim 19 , wherein:
 the first port of the serialization/deserialization circuitry is coupled with the logic circuitry via a first quantity of signal paths through the one or more first semiconductor components; and   the second port of the serialization/deserialization circuitry is coupled with the one or more conductive contacts via a second quantity of signal paths of the third semiconductor component different from the first quantity.   
     
     
         21 . The semiconductor system of  claim 20 , wherein the first quantity of signal paths comprise one or more conductive vias extending through the one or more first semiconductor components and bypassing the interface circuitry. 
     
     
         22 . The semiconductor system of  claim 19 , wherein the serialization/deserialization circuitry is configured for communicating bidirectional information signaling via the one or more conductive contacts. 
     
     
         23 . The semiconductor system of  claim 19 , wherein the third semiconductor component comprises clock circuitry having one or more first outputs coupled with the logic circuitry, one or more second outputs coupled with interface circuitry, one or more third outputs coupled with the serialization/deserialization circuitry, or a combination thereof, the clock circuitry configured to output one or more clock signals based on an oscillator of the clock circuitry, based on one or more received clock signals, or a combination thereof. 
     
     
         24 . The semiconductor system of  claim 19 , wherein the bonding of the second semiconductor component with the first side of the one or more first semiconductor components, the bonding of the third semiconductor component with the second side of the one or more first semiconductor components, or both comprise a fusion of dielectric material portions and a fusion of conductive material portions. 
     
     
         25 . A method for memory operations at a memory apparatus, comprising:
 receiving first information signaling at serialization/deserialization circuitry of a third semiconductor component that is bonded with a first side of one or more first semiconductor components, the one or more first semiconductor components comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays; and   outputting second information signaling from the serialization/deserialization circuitry to logic circuitry of a second semiconductor component based on the first information signaling, the second semiconductor component bonded with a second side of the one or more first semiconductor components, and the logic circuitry coupled with the interface circuitry and operable to access the one or more memory arrays via the interface circuitry.   
     
     
         26 . The method of  claim 25 , further comprising:
 deserializing the first information signaling from a first quantity of signal paths to provide a parallel output of the second information signaling via a second quantity of signal paths, the second quantity being greater than the first quantity.   
     
     
         27 . The method of  claim 26 , further comprising:
 receiving third information signaling at the serialization/deserialization circuitry from the logic circuitry; and   serializing the third information signaling from the second quantity of signal paths to provide a serial output of fourth information signaling via the first quantity of signal paths based on the third information signaling.   
     
     
         28 . The method of  claim 26 , wherein the deserializing is based on a clock signal received at the third semiconductor component. 
     
     
         29 . The method of  claim 25 , wherein:
 the first information signaling is received via a first quantity of signal paths of the third semiconductor component coupled with one or more conductive contacts at a surface of the third semiconductor component; and   the second information signaling is output to the logic circuitry via a second quantity of signal paths through the one or more first semiconductor components.   
     
     
         30 . The method of  claim 25 , wherein the first information signaling comprises data signaling, command signaling, or a combination thereof.