Pixel with vertical transfer gate

Abstract

The image sensor comprises a semiconductor layer and a vertical gate structure. The semiconductor layer has a first side and a second side opposite to the first side. The semiconductor layer includes a first photodiode and a second photodiode adjacent to the first photodiode. The vertical gate structure is disposed between the first photodiode and the second photodiode. The vertical gate structure includes a planar portion and a vertical gate portion. The planar portion is disposed proximate to the first side. The vertical gate portion is extended from the planar portion a depth into the semiconductor layer.

1 . An image sensor, comprising:
 a semiconductor layer having a first side and a second side opposite to the first side, the semiconductor layer including a first photodiode and a second photodiode adjacent to the first photodiode;   a floating diffusion disposed within the semiconductor layer proximate to the first side; and   a transfer gate disposed on the semiconductor layer to couple the first photodiode to the floating diffusion, the transfer gate comprising a vertical transfer gate extending a gate depth from the first side of the semiconductor layer into the semiconductor layer; and   a vertical gate structure disposed on the semiconductor layer between the first photodiode and the second photodiode, the vertical gate structure including a planar portion disposed proximate to the first side and a vertical gate portion extending a depth from the planar portion into the semiconductor layer;   wherein the gate depth is the same as the depth that the vertical gate portion of the vertical gate structure extends.   
     
     
         2 . The image sensor according to  claim 1 , wherein the transfer gate and the vertical gate structure are formed of the same composition. 
     
     
         3 . The image sensor according to  claim 2 , wherein the transfer gate and the vertical gate structure comprise polysilicon. 
     
     
         4 . The image sensor according to  claim 1 , further comprising a second vertical gate structure disposed to separate the first photodiode from a transistor region containing at least one of a row select transistor, a reset transistor, or a source follower transistor. 
     
     
         5 . The image sensor according to  claim 4 , further comprising a third vertical gate structure disposed to separate a transistor from a ground contact. 
     
     
         6 . The image sensor according to  claim 5 , wherein the vertical gate structure and the second vertical gate structure are interconnected so as to surround the first photodiode. 
     
     
         7 . The image sensor according to  claim 1 , wherein the vertical gate structure is coupled to receive a ground reference voltage or a negative bias voltage. 
     
     
         8 . The image sensor according to  claim 1 , wherein the depth of the vertical gate structure is same as the depth of the semiconductor layer. 
     
     
         9 . The image sensor according to  claim 1 , wherein the semiconductor layer is a first wafer layer including thereon the vertical gate structure and the first photodiode, and at least one of a row select transistor, a reset transistor, or a source follower transistor is disposed on a second wafer layer vertically stacked on the first wafer layer. 
     
     
         10 . The image sensor according to  claim 9 , wherein a ground contact is vertically aligned with the vertical gate structure. 
     
     
         11 . The image sensor according to  claim 10 , wherein the ground contact is coupled to the vertical gate structure through a vertical contact structure. 
     
     
         12 . The image sensor according to  claim 1 , further comprising a backside deep trench isolation structure disposed on the second side of the semiconductor layer, wherein the backside deep trench isolation structure is vertically aligned with the vertical gate structure. 
     
     
         13 . The image sensor according to  claim 12 , wherein a vertical gap is located between the vertical gate structure and the backside deep trench isolation structure. 
     
     
         14 . The image sensor according to  claim 1 , wherein the vertical gate structure is separated from the semiconductor layer by a dielectric layer. 
     
     
         15 . An image sensor, comprising:
 a first wafer comprising;
 a first semiconductor layer having a first side and a second side opposite to the second side; 
 a photodiode having a photodiode doped region, the photodiode disposed within the first semiconductor layer proximate to the first side of the first semiconductor layer; 
 a floating diffusion disposed within the first semiconductor layer proximate to the first side; 
 a transfer gate disposed on the semiconductor layer to couple the first photodiode to the floating diffusion, the transfer gate comprising a vertical transfer gate extending a gate depth from the first side of the semiconductor layer into the first semiconductor layer; and 
 a vertical gate structure disposed on the first semiconductor layer between the photodiode and a photodiode doped region of a second photodiode adjacent to the first photodiode, the vertical gate structure including a planar portion disposed proximate to the first side and a vertical gate portion extending a depth from the planar portion into the first semiconductor layer; and 
   a second wafer stacked on the first wafer comprising;
 a second semiconductor layer disposed on the first semiconductor layer; and 
 a doped region having an impurity polarity identical to that of the second semiconductor layer, the doped region coupled to receive a ground voltage; 
 wherein the doped region is coupled to the vertical gate structure. 
   
     
     
         16 . The image sensor according to  claim 15 , wherein the doped region is vertically aligned with the vertical gate structure. 
     
     
         17 . The image sensor according to  claim 16 , further comprising a vertical contact structure coupled to the doped region and the vertical gate structure. 
     
     
         18 . The image sensor according to  claim 15 , wherein the second wafer further comprises at least one of a row select transistor, a reset transistor, or a source follower transistor disposed on a second semiconductor layer. 
     
     
         19 . The image sensor according to  claim 15 , wherein the gate depth is equal to the depth that the vertical gate portion of the vertical gate structure extends. 
     
     
         20 . The image sensor according to  claim 15 , further comprising a second vertical gate structure that is disposed between the floating diffusion and a photodiode doped region of a third photodiode adjacent to the second photodiode.